Design and Verification Tools for Continuous Fluid Flow- based Microfluidic Devices Jeffrey McDaniel, Auralila Baez, Brian Crites, Aditya Tammewar, Philip.

Slides:



Advertisements
Similar presentations
Network II.5 simulator ..
Advertisements

Digital System Design Subject Name : Digital System Design Course Code : IT-314.
Computer-Aided Design for Microfluidic Chips Based on Multilayer Soft Lithography Nada Amin 1, William Thies 2, Saman Amarasinghe 1 1 Massachusetts Institute.
Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007.
1 Hardware description languages: introduction intellectual property (IP) introduction to VHDL and Verilog entities and architectural bodies behavioral,
Logic Design Outline –Logic Design –Schematic Capture –Logic Simulation –Logic Synthesis –Technology Mapping –Logic Verification Goal –Understand logic.
Copyright Arshi Khan1 System Programming Instructor Arshi Khan.
(1) Introduction © Sudhakar Yalamanchili, Georgia Institute of Technology, 2006.
Tabu Search-Based Synthesis of Dynamically Reconfigurable Digital Microfluidic Biochips Elena Maftei, Paul Pop, Jan Madsen Technical University of Denmark.
Architectural Design.
Presenter : Cheng-Ta Wu Vijay D’silva, S. Ramesh Indian Institute of Technology Bombay Arcot Sowmya University of New South Wales, Sydney.
April 15, Synthesis of Signal Processing on FPGA Hongtao
An Introduction Chapter Chapter 1 Introduction2 Computer Systems  Programmable machines  Hardware + Software (program) HardwareProgram.
Using Mathematica for modeling, simulation and property checking of hardware systems Ghiath AL SAMMANE VDS group : Verification & Modeling of Digital systems.
Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) Terms of Use Lecture 12 – Design Procedure.
COE4OI5 Engineering Design. Copyright S. Shirani 2 Course Outline Design process, design of digital hardware Programmable logic technology Altera’s UP2.
CAD Techniques for IP-Based and System-On-Chip Designs Allen C.-H. Wu Department of Computer Science Tsing Hua University Hsinchu, Taiwan, R.O.C {
Principles Of Digital Design Chapter 1 Introduction Design Representation Levels of Abstraction Design Tasks and Design Processes CAD Tools.
ASIC/FPGA design flow. FPGA Design Flow Detailed (RTL) Design Detailed (RTL) Design Ideas (Specifications) Design Ideas (Specifications) Device Programming.
Extreme Makeover for EDA Industry
Automatic Synthesis of Microfluidic Large Scale Integration Chips from a Domain-Specific Language Jeffrey McDaniel, Christopher Curtis, Philip Brisk University.
CMP 4202: VLSI System Design Lecturer: Geofrey Bakkabulindi
CSE 494: Electronic Design Automation Lecture 2 VLSI Design, Physical Design Automation, Design Styles.
COE 405 Design and Modeling of Digital Systems
Hardware/Software Co-design Design of Hardware/Software Systems A Class Presentation for VLSI Course by : Akbar Sharifi Based on the work presented in.
Galen SasakiEE 260 University of Hawaii1 Electronic Design Automation (EDA) EE 260 University of Hawaii.
Chonnam national university VLSI Lab 8.4 Block Integration for Hard Macros The process of integrating the subblocks into the macro.
Languages for HW and SW Development Ondrej Cevan.
TTCN-3 MOST Challenges Maria Teodorescu
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University
Fall 2004EE 3563 Digital Systems Design EE 3563 VHSIC Hardware Description Language  Required Reading: –These Slides –VHDL Tutorial  Very High Speed.
Electrical and Computer Engineering University of Cyprus LAB 1: VHDL.
Lecture 12: Reconfigurable Systems II October 20, 2004 ECE 697F Reconfigurable Computing Lecture 12 Reconfigurable Systems II: Exploring Programmable Systems.
EEL 4713/EEL 5764 Computer Architecture Spring Semester 2004 Instructor: Dr. Shonda Walker Required Textbook: Computer Organization & Design, by Patterson.
Johnathan Fiske, *Dan Grissom, Philip Brisk
1 Hardware description languages: introduction intellectual property (IP) introduction to VHDL and Verilog entities and architectural bodies behavioral,
Introduction to VHDL Simulation … Synthesis …. The digital design process… Initial specification Block diagram Final product Circuit equations Logic design.
Fast Online Synthesis of Generally Programmable Digital Microfluidic Biochips Dan Grissom and Philip Brisk University of California, Riverside CODES+ISSS.
IMPLEMENTATION OF MIPS 64 WITH VERILOG HARDWARE DESIGN LANGUAGE BY PRAMOD MENON CET520 S’03.
1/8/ L2 VHDL Introcution© Copyright Joanne DeGroat, ECE, OSU1 Introduction to VHDL.
1 of 16 April 25, 2006 System-Level Modeling and Synthesis Techniques for Flow-Based Microfluidic Large-Scale Integration Biochips Contact: Wajid Hassan.
Henry Selvaraj 1 Henry Selvaraj; Henry Selvaraj; Henry Selvaraj; Logic Synthesis EEG 707 Dr Henry Selvaraj Department of Electrical and Computer Engineering.
04/26/20031 ECE 551: Digital System Design & Synthesis Lecture Set : Introduction to VHDL 12.2: VHDL versus Verilog (Separate File)
Wajid Minhass, Paul Pop, Jan Madsen Technical University of Denmark
Digital Design Using VHDL and PLDs ECOM 4311 Digital System Design Chapter 1.
ASIC/FPGA design flow. Design Flow Detailed Design Detailed Design Ideas Design Ideas Device Programming Device Programming Timing Simulation Timing Simulation.
EECE 320 L8: Combinational Logic design Principles 1Chehab, AUB, 2003 EECE 320 Digital Systems Design Lecture 8: Combinational Logic Design Principles.
SUBJECT : DIGITAL ELECTRONICS CLASS : SEM 3(B) TOPIC : INTRODUCTION OF VHDL.
Programmable Hardware: Hardware or Software?
ASIC Design Methodology
Combinational Logic Design
Jeffrey McDaniel1, William H. Grover2 and Philip Brisk1
VLSI Testing Lecture 5: Logic Simulation
VLSI Testing Lecture 5: Logic Simulation
Paper Microfluidic Devices
Architecture Synthesis for Cost Constrained Fault Tolerant Biochips
Vishwani D. Agrawal Department of ECE, Auburn University
332:437 Lecture 7 Verilog Hardware Description Language Basics
Embedded systems, Lab 1: notes
ECE-C662 Introduction to Behavioral Synthesis Knapp Text Ch
Microfluidic Biochips
Design Automation for Flow-based Microfluidic BioChips
332:437 Lecture 7 Verilog Hardware Description Language Basics
HIGH LEVEL SYNTHESIS.
332:437 Lecture 7 Verilog Hardware Description Language Basics
CS 153 Logic Design Lab Professor Ian G. Harris
Design Methodology & HDL
© Copyright Joanne DeGroat, ECE, OSU
Digital Designs – What does it take
Building a model from natural language with INDRA
Presentation transcript:

Design and Verification Tools for Continuous Fluid Flow- based Microfluidic Devices Jeffrey McDaniel, Auralila Baez, Brian Crites, Aditya Tammewar, Philip Brisk University of California, Riverside Asia and South Pacific Design Automation Conference Yokohama, Japan, January 23, 2013

2 The Future Of Chemistry Miniaturization + Automation

3 Applications Biochemical assays and immunoassays Clinical pathology Drug discovery and testing Rapid assay prototyping Testing new drugs (via lung-on-a-chip) Biochemical terror and hazard detection DNA extraction & sequencing

4 Design of Continuous Fluid-flow LoCs AutoCAD Draw each layer of the chip manually Akin to transistor-level design of ICs with manual wire routing Limited Automation Multi-layer soft lithography [Amin et al., ICCD 2009] [Mihass et al. CASES 2011 & 2012] Capillary dielectrophoresis [Pfeiffer et al. TCAD 2006] [Hsieh and Ho, VLSI Design 2011] This session at ASPDAC 2013

918 micromechanical valves Multiplexer allows control of micromechanical valves by 21 external solenoid valves Design and physical layout took approximately 1 year of postdoc time (personal communication) 5 EPFL Programmable Fluidic Device [Fidalgo and Maerkl, Lab-on-a-Chip 2010]

6 Semiconductor Industry Design Principles Hardware Design Languages VHDL Verilog / SystemVerilog SystemC Verification User specifies behavioral properties to verify Synthesis and Physical Layout Synopsys, Cadence, Magma, etc. Mostly automated, but also support user interaction

A typical LoC consists of A collection of “components” Fluidic interconnect between components “Netlist”-like representation 7 Key Observation! [Amin et al., ISCA 2007]

Microfluidic Hardware Design Language (MHDL) Functional Verification, Performance Simulation 8 Our Contributions

9 MHDL Syntax Diagram One entity per component; entities may have optional external control List the components in the LoC Specify connections between components

Engineers will continually invent new components Extensible component libraries are necessary Technological (in)compatibility between components Must be part of component/library specification 10 MHDL Design Challenges [Melin and Quake, Annu. Rev. Biophys. Biomol. Struct. 2007]

Mixer 3 valves + input/output control Memory Multiplexer, Demultiplexer 11 Components, Sub-components [Urbanski et al., Lab-on-a-Chip 2006]

12 Design Flow (Revisited)

The control inputs to the components that compose an LoC form a machine language Electrical control: inputs are Boolean Solenoid (pressure) control: inputs are real-valued 13 Machine and Assembly Languages [Hong et al., J. Physics: Condensed Matter, 2006] [Unger et al., Science 2000]

A vector of control values is like a machine language instruction A sequence of vectors forms a machine language program 14 Machine and Assembly Languages [Jensen et al., Lab-on-a-Chip 2010]

Automatically derive human-readable assembly language from the netlist/machine language Turn each component on/off (etc.) Fluid transfers Machine and Assembly Languages [McCaskill and Wagler, FPL 2000] Generalizes the notion of a fluidic instruction set like AquaCore 15 [Amin et al., ISCA 2007]

16 Design Flow (Revisited)

17 Device-Specific Assembler Inputs Netlist representation of an LoC Assembly language assay specification Functional verification Can the netlist execute the assay? Is there a component to execute each operation? Are all required fluid transfers possible? Output: Device Control Program Sequence of control vectors to execute the assay

18 Simulation Performance Evaluation (Latency) Assay specification (e.g., MIX for 30s) Fluid transfer overhead Hagen-Poisseuile Equation: T = V/Q V : Volume of fluid to transfer Q : Volumetric flow rate Volumetric Flow Rate: Q = ΔPπd 4 / 128μL ΔP : Pressure drop μ : Fluid viscosity d : Channel diameter – not known until after physical layout L : Channel length – not known until after physical layout Absent layout information, the user can specify d and L

19 Example: Influenza Detection The thermocycling protocol applied to the device consists of 92 degrees C for 30s, and then 35 cycles of the following: 92 degrees C for 5s, 55 degrees C for 10s, and 72 degrees C for 20s, and finally 72 degrees C for 60s, for a total cycling time of 22 minutes. A portion of the PCR product (~60nl) is subsequently subjected to a restriction endonuclease digestion within the same device. The restriction digest reaction is performed at 37 degrees C for 10 min. [Pal et al., Lab-on-a-Chip 2005]

Example: Influenza Detection [Pal et al., Lab-on-a-Chip 2005] 20

Example: Influenza Detection 21 [Pal et al., Lab-on-a-Chip 2005]

Example: Influenza Detection [Pal et al., Lab-on-a-Chip 2005] 22

23 Conclusion and Future Work Continuous Fluid Flow LoC Specification Technology-independent MHDL language Verification and simulation framework Machine Language LoC Interface Automatically derive human-readable assembly Human specifies assay in assembly Future Work Compile high-level language to assembly Physical design flow(s)