International Master of Science Program in System-on-Chip (SoC) Design at KTH SoC Masters Axel Jantsch Royal Institute of Technology Electronic System Design Laboratory

Background

The challenge

The challenge: example u In year 2005 our students are launching a design project for I-Phone with the following properties: –Single chip phone, PDA, TV, mini-DVD recorder, GPS, and medical monitoring device inttegrated to a compact handheld device –On-chip RF (Bluetooth, GSM+, W-CDMA and local 4th generation wideband), optical I/F to home theater system –Clock internally at 2.8 GHz, externally 820 MHz, 300 MHz JTAG –135 million gates, 256Mb embedded RAM (of which 144 Mb used by 3-D engine mainly for textures) –Single 1.5 V battery (AAA), 1 month standby, 4 hour DVD, 24 h web, 2 day phone –Full user and location awareness, build-in software agents for user adaptation and network adaptation (cognitive radio) –4 Terabit all-electronic harddisk u What are the open issues? –System noise budgets (even for digital parts) –System interference of its own analog and RF functionality; deep submicron effects –Specification and design of functionality and performance characteristics –Verfication u Globalisation of the product design and industrial activities with multi-cultural and geographically distributed teams

System-on-Chip int. M.Sc. program: SoC Masters

Three Lines of Courses u Group A: Design of heterogeneous SoC architectures containing custom hardware, digital signal processors (DSP), microprocessors, and embedded software. u Group B: Physical integration and implementation of heterogeneous blocks such as hardware, analog interfaces while optimizing power consumption, performance, cost, and noise. u Group C: SoC design methodology issues such as specification and validation, integrating the separate design flows for tightly coupled hardware and software development and supporting CAD tools.

Courses u CourseCredit unitsQuarter u Hardware modeling (C)41 u Embedded systems (A)51 u Digital circuit design (B)51-2 u Digital hardware organization (A)42 u Design of fault-tolerant systems (A)42 u SoC Architectures (A)42 u Digital systems engineering (B)53 u Design documentation & IPR issues (C)43 u Anatomy of CAD tools for electronic design automation (C)53

Courses u System modeling (C)53 u Electronic system packaging (B)54 u Radio electronics (B)54 u Low power analog & u mixed signal IC´s (B)54 u System ASIC design (A)54 u Special topics in SoC (C)44 u Master's thesis (2nd year) (A-B-C)201-2