Mass production testing of the front-end ASICs for the ALICE SDD system L. Toscano a, R. Arteche Diaz b,d, S. Di Liberto b, M.I. Martínez a,c, S.Martoiu a, G. Mazza a, M.A. Mazzoni b, F. Meddi b, A. Rivetti a, F. Tosello a, G.M. Urciuoli b and R. Wheadon a a INFN Sezione di Torino, Torino, Italy b INFN Sezione di Roma, Roma, Italy c UNAM, Mexico City, Mexico d CEADEN, Havana, Cuba.

11th Workshop, Heidelberg, Sept 12-16,2005L. Toscano - INFN Torino Outline SDD overview Front-end ASICs Test criteria and test set-up Test results Conclusions

11th Workshop, Heidelberg, Sept 12-16,2005L. Toscano - INFN Torino The Inner Tracking System The ITS: six layers of silicon detectors Two layers of hybrid pixels Two layers of silicon drift detectors Two layers of double sided microstrips The SDD layers Will have 260 SDDs Total area: 1.3 m 2 About electronic channels

11th Workshop, Heidelberg, Sept 12-16,2005L. Toscano - INFN Torino SDD mechanical support The SDD mechanical support is composed by carbon-fibre cones and cylinders:  Carbon-fibre structures called ladders form two layers: 3 rd with 14 units 4 th with 22 units  Ladders supported by rings  SDD modules on ladder: detector front-end electronics  End ladder cards HV boards LV boards data compression interface with the DAQ  Microcables aluminium on Upilex TAB-style bonding rings Ladders cones

11th Workshop, Heidelberg, Sept 12-16,2005L. Toscano - INFN Torino The front-end module  The silicon drift detector 256 anodes each side  Two front-end hybrids: based on two ASICs 8 PASCAL and AMBRA  Two LV boards: power supply LVDS to CMOS parameter monitoring  One HV board: filter capacitors voltage divider The basic building block of SDD system is the module, composed by: detector front-end hybrids

11th Workshop, Heidelberg, Sept 12-16,2005L. Toscano - INFN Torino PASCAL 64 preamplifiers 64 channel SCA with 256 cells/channel bit ADCs internal test-pulse generator JTAG protocol custom low power digital interface PASCAL is a mixed-mode ASIC with 64 input channels:

11th Workshop, Heidelberg, Sept 12-16,2005L. Toscano - INFN Torino AMBRA baseline subtraction (6-bit registers) channel masking compression (10 to 8 bits) parity check (RAM & registers) multiplexing fully differential digital I/Os addressable JTAG interface AMBRA is a control, pre-processing and buffering ASIC:

11th Workshop, Heidelberg, Sept 12-16,2005L. Toscano - INFN Torino The 8-inch wafer For cost reasons both ASICs fabricated using the same set of masks IBM Commercial technology Both ICs implemented in 0.25  m CMOS Each 8-inch wafer hosts about 146 testable couples PASCAL and AMBRA AMBRA PASCAL Preselection and characterization of AMBRA and PASCAL: On-wafer tests 2 test procedures

11th Workshop, Heidelberg, Sept 12-16,2005L. Toscano - INFN Torino PASCAL test procedure (1) 1.Power consumption test:  measures Iadc, Ianlg and Idig without clock  measures repeated with clock at 40MHz  values in a reference range 2.ADC frequency test:  at 40MHz or at 20MHz programmable via JTAG  ADC current value reduced at 20MHz 3.AM frequency test:  at 40MHz or at 20MHz programmable via JTAG  internal test pulse generator  measures test pulse signal position The PASCAL chips test procedure consists of 6 tests:

11th Workshop, Heidelberg, Sept 12-16,2005L. Toscano - INFN Torino PASCAL test procedure (2) 4.Noise test:  measures the mean and rms for all channels  performed at the low gain value  parameters must be in range for all 64 channels 5.Baseline test:  sets a sweep of baseline values via JTAG  tests the baseline DAC linearity  gain values must be in range for all 64 channels 6.Signal test:  sets a sweep of test pulse values via JTAG  checks the calibration DAC linearity  gain values must be in range for all 64 channels

11th Workshop, Heidelberg, Sept 12-16,2005L. Toscano - INFN Torino AMBRA test procedure The AMBRA test procedure consists of one power consumptions test + 4 functional tests: 1.Power consumptions test:  checks the I dd at 40MHz  checks I dde 2.Logic test A:  handshake signals from/to PASCAL  data bus and flow control signals  multi event buffer mode 3.Logic test B:  10-to-8-bit compression  baseline subtraction registers 4.Memory test:  4 memory buffers  parity bit 5.JTAG test:  W\R all JTAG registers  JTAG lines from/to PASCAL

11th Workshop, Heidelberg, Sept 12-16,2005L. Toscano - INFN Torino Test system set-up Minimal changes in the hardware:  2 full custom probe cards  2 different test boards Agilent 16702B Logic Analysis System for data acquisition (TCP/IP). Test system controlled by a PC running dedicated software in LabView for data analysis 2 Agilent E3631A power supplies (GPIB) The test system set-up is based on a semiautomatic Cascade Microtech probe station with motorized chuck stage for 8-inch wafers (GPIB):

11th Workshop, Heidelberg, Sept 12-16,2005L. Toscano - INFN Torino AMBRA and PASCAL probe cards  Custom low power digital interface between AMBRA and PASCAL  On board digital buffers pseudo LVDS to LVDS standard conversion Are required:

11th Workshop, Heidelberg, Sept 12-16,2005L. Toscano - INFN Torino PASCAL selection criteria The PASCAL chips are considered: Good, all six tests are passed with no errors Grey, the first three tests are passed, at least one of the last three is not passed Bad, all other ones LabView front panel for PASCAL tests

11th Workshop, Heidelberg, Sept 12-16,2005L. Toscano - INFN Torino AMBRA selection criteria The AMBRA chips are preselected by this classification: Good, power consumption test and all four functional tests are passed with no errors Grey, power consumption test and functional tests are passed with no errors and no more than 128 memory bits are stuck Bad, all other ones LabView front panel for AMBRA tests

11th Workshop, Heidelberg, Sept 12-16,2005L. Toscano - INFN Torino PASCAL power test results (1) ADC and analogue current values of 143 good PASCAL chips in wafer ALEQARX Mean = mA  = 0.24 mA (2.0%) Mean = mA  = 3.09 mA (4.5%)

11th Workshop, Heidelberg, Sept 12-16,2005L. Toscano - INFN Torino PASCAL power test results (2) Digital current values for 143 good PASCAL chips in wafer ALEQARX with clock at 40MHz: Mean value = 52.7mA  = 0.41 mA (0.8%)

11th Workshop, Heidelberg, Sept 12-16,2005L. Toscano - INFN Torino  5069 good PASCAL channels  On one wafer  Mean value =   = (0.76%) Typical voltage gain values for baseline DAC PASCAL baseline test results good PASCAL channels On 4 wafers Mean value = 0.92  = 0.01 (1.13%)

11th Workshop, Heidelberg, Sept 12-16,2005L. Toscano - INFN Torino PASCAL Signal test results ,64244,446,849,251,6 gain-good Gain (mV/fC) gain-good Minimum Maximum 5012channels Mean 1.6Std Deviation 0.023Std Error CHANNELSCHANNELS  5012 good PASCAL channels  On one wafer  Mean value = 46.3 mV/fC   = 1.6 mV/fC (3.5%) Typical gain values for test pulse DAC good PASCAL channels On 4 wafers Mean value = mV/fC  = 1.94 mV/fC (4.1%)

11th Workshop, Heidelberg, Sept 12-16,2005L. Toscano - INFN Torino AMBRA power test results (1) Values of I dd of 63 good AMBRA chips on wafer SK8MQHX: Mean value = mA  = 0.41 mA (0.86%)

11th Workshop, Heidelberg, Sept 12-16,2005L. Toscano - INFN Torino AMBRA power test results (2) Values of I dde of 63 good AMBRA chips on wafer SK8MQHX: Mean value = 34.9 mA  = 0.5 mA (1.43%)

11th Workshop, Heidelberg, Sept 12-16,2005L. Toscano - INFN Torino PASCAL test map Wafer AXEQFNX Good = 119 -> 81% Grey = 15 -> 10.2% Bad = 13 -> 8.8% Tot = 147 First 12 wafers: Good = 89% Grey = 6% Bad = 5%

11th Workshop, Heidelberg, Sept 12-16,2005L. Toscano - INFN Torino AMBRA test map Wafer AXEQFNX Good = 114 -> 75.5% Grey = 13 -> 8.6% Bad = 24 -> 15.9% Tot = 151 First 12 wafers: Good = 73% Grey = 10% Bad = 17%

11th Workshop, Heidelberg, Sept 12-16,2005L. Toscano - INFN Torino  A mass production testing system was required to test 2400 AMBRA PASCAL for 260 SDD modules  The system is working efficiently at INFN in Rome  Typical testing times are 510 seconds for PASCAL and 220 seconds for AMBRA  89% good PASCAL chips and 73% good AMBRA chips on 12 wafers Conclusions  1.8 wafers/month  2800 PASCAL and 2400 AMBRA in February 2006  22 wafers to be tested to meet the requirements