Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis Nuno Alves, Yiwen Shi, Nicholas Imbriglia, and Iris Bahar Brown University Jennifer Dworak Southern Methodist University Kundan Nepal Bucknell University

Chips that Pass Manufacturing Test Can Fail due to Multiple Reasons in the Field Soft Errors & Noise Latent Defects & Test Escapes Wearout Knowledge of Where the Failure Occurred Can Be Very Useful Which portions of the design should be hardened in the next design iteration? In a multi-core architecture, where are other identical cores more likely to fail? How can we optimize future test sets to test for developing wearout? The Problem: Many Online Detection Schemes Provide Little Diagnostic Information

Logic Implications Capture Relationships Between Circuit Sites Implications are naturally- occurring relationships between the values at combinations of circuit sites. In the circuit on the left, N5 = 1 implies that N9 = 0. In the steady-state, this relationship should always hold if the circuit is operating correctly. N5 =1  N9 = 0

Implication Checkers Can Be Used to Monitor A Circuit for Errors A small amount of additional hardware may be added to a circuit to verify that implications are satisfied during normal circuit operation. For example, an AND gate may be used to identify the case where both N5 and N9 are equal to one, a condition that violates the implication and indicates an error. Implication Hardware for N5 =1  N9 = 0

Each Implication Can Monitor Only a Subset of the Circuit Faults P Q Direct Path P=0 → Q=0 Faults along the path may be detected P Q P=1 → Q=1 Faults along reconverging paths may be detected Reconvergent Fanout Divergent Fanout P Q Faults along paths to common ancestors may be detected Q=0 → P=0 A good subset of all implications must be chosen for monitoring with checker hardware to obtain good overall coverage at reasonable cost.

If we can identify which implication has failed, we can obtain a suspect list of faults that could have caused the failure. We need to modify the checker logic to include flip- flops at the output of each implication that save the error signals so that we can determine which implication failed and create a failure signature.

Reducing the Area Overhead: Group Implications A flip-flop is approximately four times as expensive as our standard implication checker hardware. To obtain reasonable overhead, our implications must be grouped. Several implications are fed into a single OR gate, and the error signal at the output of the OR gate is captured in a flip flop. Additional overhead may be traded for additional diagnostic resolution.

Greedy Implication Grouping Procedure We use a greedy algorithm to group implications that cover the same faults: Start with a dictionary matrix that specifies which faults are detectable by each implication. Group implications with the smallest number of mismatches (as shown in Step 1). Continue until the desired number of groups is obtained.

Application: On-Chip Test Set Selection In a multi-core architecture, other homogeneous cores may be susceptible to the same issues that caused the first core to fail. On-chip testing of other cores for the same failure mechanisms may allow problem cores to be taken offline before they fail during user operation. Tests applied should: 1) Focus on areas of the circuit that could have caused the original error 2) Provide multiple detections of the faults of interest 3) Be short to reduce the amount of power, time, etc. spent on test Diagnostic Information from Test Set Selection Can Help Us Intelligently Target Our Tests!

On-Chip Test Set Selection Procedure Test sets are selected from a test superset (in our case, a 15-detect test set). Short test tests to be applied if a given implication failed are determined a priori and the results stored in the Implication Assignment Table. On an implication failure, the failing bit(s) in the implication failure signature are compared to the bits in the implication assignment table, and patterns are selected. The selected patterns are used to test all identical cores.

Number of Detections for Suspect Faults during Test For each circuit, an implication set corresponding to approximately 10% hardware overhead was obtained according to the method in [1]. Test Supersets consisting of 15 detect test sets were obtained from Mentor Graphics FastScan. The number of test patterns selected on an implication failure is 20. The chart above shows the minimum, maximum, and average number of detections for each suspect fault by the 20-pattern test subset selected on the corresponding implication failure averaged across all implications in the checker hardware. Significant detections are obtained even with very short test sets!

Average Suspect List Size For Grouped/Ungrouped Checkers Checker logic was grouped so that the ratio of flip- flops to implication checkers is approximately four. The average size of the suspect lists is shown in the figure to the left. Comparison to Logic Duplication We also analyzed the diagnostic resolution obtained when the failing output is identified through logic duplication and output comparison. The graph shows the size of the suspect fault list and the number of detections of each targeted fault. The suspect list is larger than with implications and the number of detections during test is lower.

Conclusions Because logic implications cover only a relatively small portion of the circuit, they can often provide very good diagnostic resolution when a failure occurs. Once suspect failure locations are identified, they can be targeted explicitly during on-chip test. Our methods allow us to select very short sets of test patterns on an implication failure that can detect suspect faults multiple times—in some cases 20 times for a 20-pattern test set. [1] N. Alves, A. Buben, K. Nepal, J. Dworak, and R. I. Bahar, “A Cost Effective Approach for Online Error Detection Using Invariant Relationships, IEEE Transactions on CAD, vol. 29, no. 5, pp , May 2010

Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis

Nuno Alves, Yiwen Shi, Nicholas Imbriglia, and Iris Bahar Brown University, Providence, RI, USA Jennifer Dworak Southern Methodist University, Dallas, TX, USA

Kundan Nepal Bucknell University, Lewisburg, PA, USA