EE141 1 Electronic Design Automation [ Adopted from Jan M. Rabaey, Alessandra Nardi, Abhay Dixit, Meeta Bhate, Kedar Rajpathak, Tulika Mitra]

EE141 2 Electronic Design Automation  Design Analysis  Structural and Behavioral Modeling in HDL  Design Verification  Cell Based Design  Programmable Logic Devices and FPGA  Design Synthesis

EE141 3 Design methodologies  analysis and verification - simulation is input dependent - verification requires understanding of circuit operation  implementation and synthesis  testability tools and techniques

EE141 4 Terminology  HDL: Hardware Description Language  E.g.: Verilog, VHDL  RTL: Register Transfer Level. It is HDL written for logic synthesis: clock cycle to clock cycle operations and events are explicitly defined  architecture of the design is implicit in RTL code  Behavioral HDL It is HDL written for behavioral synthesis: it describes the intent and the algorithm behind the design  Behavioral synthesis It tries to optimize the design at architectural level with constraints for clock, latency and throughput. The output is RTL level design with clocks, registers and buses.  Logic synthesis It automatically converts RTL code into gates without modifying the implied architecture. It tries to optimize the gate-level implementation to meet performance (timing, area….) goals

EE141 5 Verification at different levels of abstraction Goal: Goal: Ensure the design meets its functional and timing requirements at each of these levels of abstraction In general this process consists of the following conceptual steps: 1. Creating the design at a higher level of abstraction 2. Verifying the design at that level of abstraction 3. Translating the design to a lower level of abstraction 4. Verifying the consistency between steps 1 and 3 5. Steps 2, 3, and 4 are repeated until tapeout

EE141 6 Verification at different levels of abstraction Behavior al HDL System Simulators HDL Simulators Code Coverage Gate-level Simulators Static Timing Analysis Layout vs Schematic (LVS) RTLGate- level Physical Domain Verification

EE141 7 Verification Techniques functionaltiming  Simulation (functional and timing)  Behavioral  RTL  Gate-level (pre-layout and post-layout)  Switch-level  Transistor-level functional  Formal Verification (functional) timing  Static Timing Analysis (timing) Goal: Goal: Ensure the design meets its functional and timing requirements at each of these levels of abstraction

EE141 8 Classification of Simulators Logic Simulators Emulator-basedSchematic-basedHDL-based Event-drivenCycle-basedGateSystem

EE141 9 Classification of Simulators  HDL-based  HDL-based: Design and testbench described using HDL  Event-driven  Cycle-based  Schematic-based  Schematic-based: Design is entered graphically using a schematic editor  Emulators  Emulators: Design is mapped into FPGA hardware for prototype simulation. Used to perform hardware/software co-simulation.

EE Instruction Set Architecture Design (Microarchitecture Design-I) System-Level Design RTL Level Design (Microarchitecture Design II) Compiler Design Code Optimizer Hardware Design Switch Level Design Circuit Level design ISA Simulator System Level Simulator RTL Level Simulator Switch Level Simulator Circuit Level Simulator Arch./Compiler Design Toolset Processor Architecture Simulation and Design Flow Diagram HDL (VHDL or Verilog) Code Generator

EE (Some) EDA Tools and Vendors  Behavioral synthesis  Behavioral compiler  Synopsys  Logic Synthesis  Design Compiler  Synopsys  BuildGates  Ambit Design Systems  Galileo (FPGA)  Examplar (Mentor Graphics)  FPGAExpress (FPGA)  Synopsys  Synplify (FPGA)  Synplicity

EE (Some) EDA Tools and Vendors  Logic Simulation  Scirocco (VHDL)  Synopsys  Verilog-XL (Verilog)  Cadence Design Systems  Leapfrog (VHDL)  Cadence Design Systems  VCS (Verilog)  Chronologic (Synopsys)  Cycle-based simulation  SpeedSim (VHDL)  Quickturn  PureSpeed (Verilog)  Viewlogic (Synopsys)  Cobra  Cadence Design Systems  Cyclone  Synopsys

EE Circuit Simulation  Formulation of circuit equations  STA, MNA  Solution of linear equations  LU factorization, QR factorization, Krylov Methods  Solution of nonlinear equations  Newton’s method  Solution of ordinary differential equations  One-step and Multi-step methods  AC Analysis and Noise  Simulation Techniques for RF  Shooting-Newton  Harmonic-Balance

EE Analog Circuits – A World Apart  Analog circuits’ behavior specified in terms of complex functions: time-domain, frequency-domain, distortion, noise, power spectra….  Required accuracy of models much higher than digital  …emerging paradigm: Field Programmable Analog Array for prototyping (and more)

EE Design analysis and simulation  Spice - exact but time consuming  discrete time steps  circuit models  timing simulation with partitioning and relaxation method

EE Timing Simulation

EE Switch-Level Simulation  Linear Switch-Level Simulation  RSIM (Terman), nRSIM (Chu), IRSIM (Horowitz)  Model transistor as switched, linear resistor  Ternary (0, 1, X) node states  Elmore (RC product) model of circuit delay a a  1 X 0 Voltage Logic Value

EE Switch-Level Simulation Switch level model of inverter

EE Event-driven Simulation  Event: change in logic value at a node, at a certain instant of time  (V,T)  Event-driven: only considers active nodes  Efficient  Performs both timing and functional verification  All nodes are visible  Glitches are detected  Most heavily used and well-suited for all types of designs

EE Event-driven Simulation Event: change in logic value, at a certain instant of time  (V,T) D=2 a b c Events: Input: b(1)=1 Output: none D=2 a b c Events: Input: b(1)=1 Output: c(3)=0 3

EE Event-driven Simulation  Uses a timewheel to manage the relationship between components  Timewheel  Timewheel = list of all events not processed yet, sorted in time (complete ordering)  When event is generated, it is put in the appropriate point in the timewheel to ensure causality

EE Event-driven Simulation d b(1)=1 d(5)=1 D= D=2 a b c e c(3)=0 d(5)= e(4)=0 6 e(6)=1

EE Cycle-based Simulation  Take advantage of the fact that most digital designs are largely synchronous  Synchronous circuit: state elements change value on active edge of clock  Only boundary nodes are evaluated Internal Node Boundary Node LatchesLatches LatchesLatches

EE Cycle-based Simulation  Compute steady-state response of the circuit  at each clock cycle  at each boundary node LatchesLatches LatchesLatches Internal Node

EE Cycle-based versus Event-driven  Cycle-based:  Only boundary nodes  No delay information  Event-driven:  Each internal node  Need scheduling and functions may be evaluated multiple times  Cycle-based is 10x-100x faster than event-driven (and less memory usage)  Cycle-based does not detect glitches and setup/hold time violations, while event-driven does

EE Simulation: Perfomance vs Abstraction.001x SPICE Event-driven Simulator Cycle-based Simulator 1x10x Performance and Capacity Abstraction Timing Simulator

EE Perspective on accuracy and speed

EE Gate level simulation  faster than switch level  functional simulation  VHDL description used

EE Epics PowerMill *** Current information is calculated from 5.00 ns to ns *** average current on VDD : mA peak current on VDD : mA at ns rms current on VDD : mA average current on GND : mA peak current on GND : mA at ns rms current on GND : mA

EE PowerMill Performance

EE Avant!s STAR-ADM (previously Anagram)  Mixed analog/digital simulation  Claims to be more accurate for deep sub-micron design than switch-level simulation

EE Performance Benchmarks

EE Structural model in VHDL

EE Behavioral model in VHDL

EE High level behavioral VHDL

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EE Digital Systems Verification  Overview  Cycle-based and event-driven simulation  Formal methods  Timing Analysis  Hardware Description Languages (Verilog- VHDL)  System C

EE Verification - Simulation Consistency: same testbench at each level of abstraction Behavioral Gate-level Design (Post-layout) Gate-level Design (Pre-layout) RTL Design TestbenchSimulation

EE Formal Verification  Can be used to verify a design against a reference design as it progresses through the different levels of abstraction  Verifies functionality without test vectors  Three main categories:  Model Checking: compare a design to an existing set of logical properties (that are a direct representation of the specifications of the design). Properties have to be specified by the user (far from a “push-button” methodology)  Theorem Proving: requires that the design is represented using a “formal” specification language. Present-day HDL are not suitable for this purpose.  Equivalence Checking: it is the most widely used. It performs an exhaustive check on the two designs to ensure they behave identically under all possible conditions.

EE Digital Systems Verification Timing Analysis  Not only has the design to “function properly”….it also has always tighter timing constraints  Design timing properties have to be verified  Static Timing Analysis is the main method

EE Static Timing Analysis  Suitable for synchronous design  Verify timing without testvectors  Conservative with respect to dynamic timing analysis Latches Combinational Logic

EE Static Timing Analysis  Inputs:  Netlist, library models of the cells and constraints (clock period, skew, setup and hold time…)  Outputs:  Delay through the combinational logic  Basic concepts:  Look for the longest topological path  Discard it if it is false

EE Conventional Simulation Methodology Limitations  Increase in size of design significantly impact the verification methodology in general  Simulation requires a very large number of test vectors for reasonable coverage of functionality  Test vector generation is a significant effort  Simulation run-time starts becoming a bottleneck  New techniques:  Static Timing Analysis  Cycle-based simulation  Formal Verification

EE New Verification Paradigm  Functional: cycle-based simulation and/or formal verification  Timing: Static Timing Analysis Gate-level netlist RTL Testbench Logic Synthesis Cycle-based Sim. Event-driven Sim. Static Timing Analysis Formal Verification

EE More issues  System Level Simulation (Hardware/Software Codesign)  CoCentric System Studio  Synopsys  Virtual Component Co-Design (VCC)  Cadence Design Syst.  Mixed-Signal Simulation  Verilog-AMS

EE Design verification  checking number of inversions between two C 2 MOS gates  checking pull-up and pull down ratio in pseudo-NMOS gates  checking minimum driver size to maintain rise and fall times  checking charge sharing to satisfy noise- margins Electrical verification

EE Design verification  Spice too long simulation time  RC delay estimated using Penfield- Rubinstein-Horowitz method  identification of critical path (avoid false paths) Timing verification

EE Design verification  components described behaviorally  circuit model obtained from component models  resulting circuit behavior computed with design specifications  no generally acceptable verifier exists Formal verification

EE Physical issues verification (DSM)  Interconnects  Signal Integrity  P/G integrity  Substrate coupling  Crosstalk  Parasitic Extraction  Reduced Order Modeling  Manufacturability and Reliability  Power Estimation

EE (Some) EDA Tools and Vendors  Formal Verification  Formality  Synopsys  FormalCheck  Cadence Design Systems  DesignVerifyer  Chrysalis  Static Timing Analysis  PrimeTime  Synopsys (gate-level)  PathMill  Synopsys (transistor-level)  Pearl  Cadence Design Systems

EE Summary  Conventional design and verification flow review  Verification Techniques  Simulation –Behavioral, RTL, Gate-level, Switch-level, Transistor- level  Formal Verification  Static Timing Analysis  Emerging verification paradigm  Functional: cycle-based, formal verification  Timing: Static Timing Analysis

EE “Prototyping” Techniques in Design Stages time HardwareDesignChanges SoftwareSimulation Emulation PrototypeReplication Flexibility Performance Cost

EE Implementation approaches

EE Custom circuit design  labor intensive  high time-to-market  cost amortized over a large volume  reuse as a library cell  was popular in early designs  layout editor, DRC, circuit extraction

EE Layout editor  transistor symbols  relative positioning  compaction  stick diagram description  design rules automatically satisfied  automatic pitch matching 1. Polygon based (Magic) 2. Symbolic layout

EE Automatic pitch matching

EE Design rule checking  on-line DRC - rules checked and errors flagged during layout  batch DRC - post design verification

EE Circuit extraction  Circuit schematic derived from layout  Transistors are build with proper geometry  Parasitic capacitances and resistances evaluated  Extraction of inductance requires 3D analysis

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EE Cell-based design  reduced cost  reduced time  reduced integration density  reduced performance  standard cell  compiled cells  module generators  macro cell place and route

EE Standard cell  library contains basic logic cells - inverter, AND/NAND, OR/NOR, XOR/NXOR, flip-flop, AOI, MUX, adder, compactor, counter, decoder, encoder,  fan-in and fan-out specified  schematic uses cells from library  layout automatically generated

EE Standard cell  cells have equal heights  cell rows separated by routing channels

EE Standard cell design

EE Standard cell layout and description

EE An Example Cell  A 2-input dynamic C with a clearing input and an inverting output (C_dic2)

EE Single vs Double Height Cells  arbiter

EE Single vs Double Height Cells…  arbiter_dblht

EE Existing Design Flow Synopsys Synthesis Cadence Silicon Ensemble Cadence Composer Schematic Cadence Virtuoso Layout Existing Datapath Layout Behavioral Verilog Code Your Libraries LVS Verilog-XL Behavioral Verilog Structural Verilog Circuit Layout

EE New Design Flow Cadence to Synopsys Interface Cadence Silicon Ensemble Cadence Composer Schematic Cadence Virtuoso Layout Existing Datapath Layout Standard Cell Libraries LVS Verilog-XL Structural Verilog Circuit Layout

EE Placed and Routed

EE What are Standard Cell Libraries  Standard-cell libraries are fixed set of well-characterized logic blocks.  Basic logic functions are used several times on the same integrated circuit.  It will have leaf cells ranging from simple gates to latches and flip-flops. These can then be used to build arithmetic blocks like adders and multipliers.  ASIC designers commonly employ the use of standard cell libraries due to their robustness and flexibility resulting in quick turnaround times.

EE Advantages of standard cell libraries  Designers save time and money by reducing the product development cycle time.  Reduce risk by using predesigned, pretested and precharacterised standard cell libraries.  Optimisation is possible.

EE Disadvantages of standard cell libraries  Time and expenses of designing or buying the standard cell library.  Time needed to fabricate all layers of ASIC for each new design  when the standard cell library must be ported to a new fabrication process, the physical layout of all the cells need to be changed.  There are no naming conventions  There are no standards for cell behavior

EE Standard cell  large design cost amortized over a large number of designs  large number of different cells with different fan-ins  large fan-out for cells to be used in different designs  synthesis tools made standard cell design popular  standard cell design outperform PLA in area and speed  standard cell benefit from multi level logic synthesis

EE Classification of standard cell libraries  Classical Libraries: --- Theses are the most common logic elements like gates, flip-flops, multiplexers, PAL, memories etc.  IP (Intellectual Property) offerings: --- These include products like gate arrays and CPLDs which are IP offerings by many companies. Each one providing its own features and facilities in the product.

EE Fragment of an ASIC Library

EE  MOSIS compatible cell libraries are provided by many organisations, commercial and non-commercial both  Commercial organisations are: Mentor Graphics, Cadence, Artisan, Avant, Barcelona Design, Tanner Research, LEDA systems etc.  Non Commercial Organisations are:MSU’s SCMOS Library, LASI, Ballistic, Magic etc. MOSIS compatible design tools and cell libraries

EE Standard Cells Provided by Mentor Graphics  There are over 200 standard cells available for the 2.0 um, 1.2 um, and 0.8 um technology. -- 2, 3, and 4-input AND, NAND, OR, NOR, AO -- 2-input XOR and XNOR gates MUX gate -- multiple drive strength buffers, inverters and tri-state buffers -- four D-type flip-flops: dff, dffs, dffr, and dffsr -- four D-type latches: latch, latchs, latchr, latchsr  All of these cells have quickpart models with timing for full, backannotated simulation after layout

EE MGC Digital Libraries

EE MGC Digital Libraries (Contd..)

EE MGC Digital Libraries (Contd..)

EE MGC Digital Libraries (Contd..)

EE MGC Digital Libraries (Contd..)

EE New Trends in Standard Cell Libraries  In a bid to improve the performance of standard-cell designs, vendors of place-and-route and synthesis tools and cell libraries are teaming up to develop a technique that is likely to lead to the death of the standard cell itself.  Prolific Inc. (Newark, Calif.) has launched a tool called Liquid Libraries that will create tuned cells on the fly and insert them into the libraries used by place and route tools  Hot on the heels of Prolific's launch, Cadabra Design Automation (Santa Clara, Calif.) is working on a new flow that would ultimately move library generation as far forward as the synthesis phase, giving logic designers the ability to tune parts of a design for low power consumption or speed

EE New Trends Contd..  Prolific is working with Cadence Design Systems, Magma Design Automation, Monterey Design Systems and Sapphire Design Automation..  Cadabra is working with Avanti, Cadence, Synopsis and Magma.  The first fruit of the Cadabra project will be the power and performance optimization (PPO) flow.

EE Important Links to Standard Cell Libraries a) Tanner Inc. b) Prolific Inc. www. prolificinc.com c) MOSIS organisation MOSIS/Tech Support/MOSIS Compatible Design Tools d) Cadabra Design Automation Inc. e) Cadence Design Systems Inc.

EE Compiled cell  cell layout generated on the fly  transistor or gate level netlist used with transistor size specified  layout densities approach that of human designers Circuit schematics with transistor sizing

EE Compiled cell Generated layout

EE Module generators  logic level cells not efficient for subcircuit design - shifters, adders, multipliers, data paths, PLAs, counters, memories  Macrocell generators - use design parameters like number of bits  data path compilers - use bit slice modules and repeat them N times - generate interconnections between modules

EE Datapath compilers Feedtroughs used to improve routing

EE Datapath compilers Datapath compiler results

EE Macrocell place and route  channel routing - metal 2 horizontal segments metal 1 vertical segments  over the block routing (3-6 metal layers used)

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EE Array-based design implementation  mask programmable arrays  fuse based FPGAs  nonvolatile FPGAs  RAM based FPGAs To avoid slow fabrication process which takes 3-4 weeks :

EE Mask programmable arrays  gate-array - similar to standard cell  sea-of-gate - routed over the cells (high density) - wires added to make logic gates  challenge in design is to utilize the maximum cell capacity  utilization < 75% for random logic design

EE Fuse-based PLD’s

EE Fuse-based FPGA’s Actel sea-of-gate and standard cell approach

EE Fuse-based FPGA’s Example : XOR gate obtained by setting : A=1, B=0, C=0, D=1, SA=SB=In1, S0=S1=In2

EE Fuse-based FPGA’s Anti-fuse provides short (low resistance) when blown out

EE Nonvolatile FPGA’s  programming similar to PROM  erasable programmable logic devices - EPLD  electrically erasable - EEPLD  design partitioned into macrocells  flip-flops used to make sequential circuits  software used to program interconnections to optimize use of hardware  input specified from schematics, truth tables, state graphs, VHDL code

EE

EE RAM based (volatile) FPGA’s  programming is fast and can be repeated many times  no high voltage needed  integration density is high  information lost when the power goes off

EE XILINX FPGA’s  configurable logic blocks CLBs used  five input two output combinational blocks  two D flip flops are edge or level triggered  functionality and multiplexers controlled by RAM  RAM can be used as look-up table or a register file

EE XILINX FPGA’s

EE XILINX FPGA’s  each cell connected to 4 neighbors  routing channels provide local or global connections  switching matrices(RAM controlled) are used for switching between channels

EE XILINX FPGA’s

EE XILINX FPGA’s (XC4025)  32 × 32 CLBs  gates  422 k bites of RAM  operates at 250 MHz  32 kbit adder uses 62 CLBs

EE XILINX FPGA’s (XC4025)

EE Universal Nanoscale Architecture  Beyond lithographic limits  Crossed Wire nanoarrays  Implement PLAs, memory, and xbars NSC’02: to appear IEEE TR Nano

EE Design synthesis

EE Circuit synthesis  derivation of the transistors schematics from logic functions - complementary CMOS - pass transistor - dynamic - DCVSL (differential cascode voltage switch logic)  transistor sizing - performance modeling using RC equivalent circuits- layout generation  synthesis not popular due to designers reluctance

EE Logic synthesis  state transition diagrams, FSM, schematics, Boolean equations, truth tables, and HDL used  synthesis - combinational or sequential - multi level, PLA, or FPGA  logic optimization for - area, speed, power - technology mapping

EE Logic optimization  Expresso - two level minimization tool (UCB)  state minimization and state encoding  MIS - multilevel logic synthesis (UCB) Example : S = (A  B) C i C o = AB + AC i + BC i

EE Architecture synthesis  behavioral or high level synthesis  optimizing translation e.g. pipelining  Cathedral and HYPER tools  HYPER tutorial and synthesis example:

EE Architecture Synthesis Automatic Tool Application Customized Architecture Power Size Performance Timing

EE Architecture synthesis example

EE Architecture synthesis

EE Tensilica: Xtensa Architecture Copyright: Tensilica

EE Design Framework Copyright: Tensilica

EE Silicon Choices  ASIC implementation of Processor  Fast but not flexible  Time intensive design process  Example: Tensilica, HP-STMicroelectronics  Processor core in ASIC but instruction set extensions in reconfigurable logic  Medium speed but flexible  Fast design process  Example: Triscend Configurable System-on-Chip

EE Triscend Configurable SoC Copyright: Triscend

EE Reconfigurable Computing 101  Higher performance than software with higher level of flexibility than hardware  e.g. Field Programmable Gate Arrays (FPGA)  Logic Blocks –Array of computational elements whose functionality is determined through multiple SRAM configuration bits  Interconnection –Logic blocks are connected using programmable routing resources  Any custom circuit can be mapped to FPGA by computing logic functions within logic blocks and using configurable routing to connect the logic blocks together  Dynamically reconfigurable Logic  Logic reconfiguration during application execution  Temporal partitioning of software reduces logic area  Overhead for reconfiguration

EE Use of Reconfigurable Computing  Two choices  Map both control and datapath to RC  Map only datapath to RC  Granularity of reconfigurable logic  Bit  Multiple bits  ALU

EE RC Coupled to I/O System Bus  Most common form of commercial RC  Overhead of data transfer between CPU and RC  Requires large granularity of computation on RC CPU RC I/O Memory Local Bus PCI Bus Local Bus

EE RC Coupled to Local Bus  Pilchard from Chinese University of Hong Kong  Still requires large granularity of computation CPU RC I/O Memory Local Bus PCI Bus Local Bus

EE RC Coupled to CPU as Coprocessor  Tight coupling between CPU and RC  RC can execute ISA extensions  CPU and RC cannot share register file CPU RC I/O Memory Local Bus PCI Bus Local Bus

EE PICO Architecture Copyright: Bob Rau et. al.

EE Design Framework Copyright: Bob Rau et. al.

EE Design Flow Copyright: Bob Rau et. al.

EE Hardware/software Co-design  Well studied problem. Then what’s new?  High Level Synthesis (HLS)  Time-to-market constraint forces automated generation of reconfigurable bitstream from high level specification or software  Automated generation of interface  Spatial and temporal partitioning  Partitioning among multiple configurable devices  Map a function that exceeds the available space of reconfigurable device using time sharing  Requires new compilation techniques

EE High Level Synthesis-1  High level hardware description language  Start from software programming language and add support for  Parallelism via threads  Message passing  Examples: Handel-C, SystemC  Make current HDL more abstract  Superlog, System Verilog  Still requires user to find parallelism

EE High Level Synthesis-2 High Level Synthesis-2  Combine research in two different fields: compiler and design automation  Traditional HLS techniques target ASIC implementation  RC does not have the layout freedom  Objective of RC is to minimize execution time  Temporal partitioning if insufficient area  Hardware library of operators or structures commonly used by software programs

EE High Level Synthesis-3  Concentrate on loops  Leverage parallelizing compiler technology combined with high level synthesis  Parallelize computation  Optimize external memory access  Loop transformation: Area versus Performance –Unroll and Jam –Loop unrolling –Software pipelining –Loop-invariant code motion –Data layout  Hardware specific optimizations  Bitwidth reduction