L. Karklin, S. Mazor, D.Joshi1, A. Balasinski2, and V. Axelrad3 SPIE’02 ml4691-24 Sub-wavelength Lithography: An Impact of Photo Mask Errors on Circuit Performance L. Karklin, S. Mazor, D.Joshi1, A. Balasinski2, and V. Axelrad3 1Numerical Technologies, Inc., USA, 2Cypress Semiconductor, USA, and 3Sequoia Design Systems, USA

Agenda Introduction Experimental conditions Results and discussion Simulation flow Sensitivity analysis Monte Carlo simulation of mask CD errors Results and discussion Lithography data Device and circuit simulation Summary

The sub-wavelength era impacts the full design-to-manufacturing flow Above Wavelength What is drawn in design is printed on Silicon - “WYSIWYG” LAYOUT MASK SILICON WAFER = SubWavelength MASK SILICON WAFER LAYOUT The subwavelength challenge needs to be addressed throughout the IC design-to-manufacturing flow. An easy way to understand the change from above wavelength manufacturing to subwavelength, is to note the change in a long-standing relationship amongst the key components of the design-to-manufacturing flow. In particular, the layout, mask, and the silicon wafer all used to be “equal”. If you generated a square in the layout, you would also generate a square on the mask, that in turn would produce a square on silicon. Below wavelength, these objects are no longer equal due to process distortions and the introduction of new technologies, OPC and PSM to produce subwavelength features. Note that all physical layout and verification tools are based upon an assumtion of equality as are mask inspection and repair tools. This new setting requires that additional information about the silicon wafer process be transferred upstream to the physical design and mask manufacturing areas and that the tools are available in these areas to utilize the new information.

The photomask is the most critical link in that flow We need new design software and infrastructure to account for process effects and distortions from design through final device  ITRS 2001, SEMATECH DESIGN LAYOUT MASK MASK SILICON DEVICE The photomask is the most critical link in that flow

Simulation flow MASK DESIGN LAYOUT SILICON DEVICE MASK LAYOUT SILICON

Experimental flow Litho data Sensitivity analysis Device and circuit simulation

Experimental flow ICWB SDD NA, s, RET Device Parametric Yield Photo Mask CD Distribution Wafer CD Distribution ICWB NA, s, RET Wafer CD Distribution Device Parameters SDD Device Parametric Yield Circuit (Ring Oscillator) C:\Circuit.ppt

Lithography options l=248 nm (KrF) and l= 193 nm (ArF); Design Rules: Design: An Isolated line CD=80 nm , Dense lines pitch=220nm Target CD =70 nm (in resist, all dimensions are on wafer scale) l=248 nm (KrF) and l= 193 nm (ArF); 4x Reduction mask; NA=0.75; Conventional (circular) Illumination: s=0.75; RET used: Annular Illumination: sin= 0.60; sout= 0.80; Scatter Bars: 40 nm, optimized placement (based on min. MEF) PSM: EAPSM, Phase=180°, T=10%

Simulated device behaviors 70 nm MOSFET Lpoly 70nm Lpoly ± 5nm variation Affects device characteristics: IdSat decreases 10% Vth increases 4% (short channel) SEQUOIA Design device simulation Lpoly is largest factor for variability IdSat 71% of variability Vth 84% of variability D % from DLpoly -83% 71%

Sensitivity analysis 70 nm MOSFET Lpoly SEQUOIA Design Systems’ Sensitivity Analysis estimates device variability for a given level of manufacturing control For a 70nm device we obtain: Vth=340mV±13mV Idsat=1mA±0.09mA

Variability sources Vth Idsat Main source of variability is CD Control (Lpoly) Lpoly responsible for 71% of Vth variability Lpoly responsible for 84% of Idsat variability Vth Idsat

Lpoly (Gate) CD variations Gaussian Distribution 10,000 Samples 3s = 20 nm, 40 nm; -3s +3s Lpoly

Mask Yield Projections - Historical Base Slide courtesy of Brian Grenon, Grenon Consulting, Inc.

Mask CD uniformity 10 nm on wafer 5 nm on wafer Data courtesy of Anja Rosenbusch, Etec Systems Inc., an Applied Materials Company

Mask CD distribution (CD errors) CD mean -3s +3s Gaussian Distribution: 10,000 samples 3s= 20 nm* 3s= 40 nm* * Mask Scale (4x)

Lithography data

Mask CD distribution mapped to the wafer CD distribution Wafer CD distribution depends on the lithography options used

Mask linearity data Design [nm] Wafer [nm]

MEF data for 248 nm lithography

MEF data for 193 nm lithography

Simulated wafer CD distribution 193 nm Annular 193 nm Circular +/- 3s +/- 3s 248 nm Annular 248 nm Circular

Device and circuit simulation

Wafer CD (Lpoly) distribution translated to MOSFET Vth distribution

Wafer CD (Lpoly) distribution translated to ring oscillator speed

Statistical analysis of the simulated data Using SDD one can calculate a fractional yield based on custom specifications

Ring oscillator frequency distribution 3s=20 nm* 3s=40 nm* * On the 4x Mask

Summary We presented a comprehensive method by which to evaluate the layout/mask dependent device and circuit performance for different lithography options. We simulated large numbers of random mask errors and propagated these data through the virtual MOSFET manufacturing pipeline by using fast lithography and device simulators linked together. Using statistical analysis we estimated the impact of mask CD errors (3s) and lithography options (RET) on the printed wafer data and final circuit (RO) performance. Proposed methodology can be applied either to simulated data or to experimental data.