On-Chip Inductance Extraction - Concept & Formulae – 2002 On-Chip Inductance Extraction - Concept & Formulae – 2002. 3 Hyungsuk Kim hyungsuk@cae.wisc.edu

OutLine Introduction – On-Chip Inductance Loop Inductance and Partial Inductance Closed Forms of Inductance Formulae Self Inductance Formulae - Hoer, FastHenry, Ruehli, Grover Mutual Inductance Formulae - Hoer (FastHenry), Ruehli, Grover Computational Results Conclusion

Introduction – On-Chip Inductance As the clock frequency grows fast, the reactance becomes larger for on-chip interconnections Z = R + jwL w is determined not by clock frequency itself but by clock edge w ~ 1/(rising time) More layers are applied, wider conductors are used Wide conductor => low resistance Multiple layer interconnections make complex return loops Inductance is defined in the closed loop in EM

Loop Inductance Loop inductance is defined as the induced magnetic flux in the loop by the unit current in other loop Ij Loop i Loop j where, represents the magnetic flux in loop i due to a current Ij in loop j The average magnetic flux can be calculated by magnetic vector potential Aij where, ai represents a cross section of loop i

Loop Inductance (cont’d) The magnetic vector potential A, defined by B = A, has an integral form So, loop inductance is

Partial Inductance Problems of loop inductance Partial inductance The loops (called return paths) are hardly defined explicitly in VLSI In most cases, the return paths are multiple Partial inductance proposed by A. Ruehli The return path is assumed at infinite for each conductor segment It can be directly appliable to circuit simulator like SPICE 1 2 3 4 5

Partial Inductance (cont’d) Loop inductance between loop i and j is (assume loop i consists of K segments and loop j does M segments) So, loop inductance is

Partial Inductance (cont’d) Definition of partial inductance The sign of partial inductance is not considered So, partial inductance is solely dependent of conductor geometry Sign rule for partial inductance where, Skm = +1 or –1 The sign depends on the direction of current flow in the conductors

Geometry and Formulae Inductance Formulae Conductor Geometry Self Inductance : Grover(1962), Hoer(1965), Ruehli(1972), FastHenry(1994) Mutual Inductance : Grover(1962), Hoer(FastHenry)(1965), Ruehli(1972) x z T W l Conductor 1 Conductor 2 Dz Dx y Dy (a) Single Conductor (b) Two Parallel Conductors

Self Inductance Grover’s Formula Grover 2 (without table) T/W logee 0.2 0.00249 0.5 0.00211 0.8 0.00181 0.05 0.00146 0.3 0.00244 0.6 0.00197 0.9 0.00178 0.1 0.00210 0.4 0.00228 0.7 0.00187 1.0 0.00177 Grover 2 (without table)

Self Inductance (cont’d) Hoer’s Formula where

Self Inductance (cont’d) Ruehli’s Formula where If T/W < 0.01

Self Inductance (cont’d) FastHenry’s Formula where

Comparisons of Self Inductance Formula Short Conductor (l/W < 10) Medium Conductor (10 < l/W < 1000) Long Conductor (l/W > 1000) Hoer O X FastHenry Ruehli Ruehli (T=0) O (30% larger) (T/W < 0.01) Grover Grover2

Mutual Inductance Ruehli’s Formula Grover’s Formula (single filament) where where

Mutual Inductance (cont’d) Hoer’s Formula (multiple filaments) where

Conclusion On-Chip inductance becomes a troublemaker in high-performance VLSI design Higher clock frequency, wide interconnections, complex return paths The concept of partial inductance is useful in VLSI area Not related to the return path Only dependent of geometry Several inductance formulae are in hand but they have Different computational complexities Different applicable ranges according to the geometry