Memory Management Ch.8

Continuous Allocation Mem. Manegment (/strategies) Methods Continuous Allocation (Fixed-partition allocation) Multiple-partition method (variable size method) Paging (Basic Method) Hierarchical Page Hashed Page Inverted Page Segmentation

Exercise 8.1 Explain the difference between internal and external fragmentation.

Exercise 8.16 Given five memory partitions of 100 KB, 500 KB, 200 KB, 300 KB, and600 KB (in order), how would each of the first-fit, best-fit, and worst-fit algorithms place processes of 212 KB, 417 KB, 112 KB, and 426 KB (in order)? Which algorithm makes the most efficient use of memory?

Paging Hardware (fig 8-7)

Paging Example (fig 8-9) Given: N=2 bits M=4 bits Page size=4 B Physical mem. Size=32 B # of pages= 8 pages >>How to convert from logical address to physical address in paging??? Physical address = base address+ offset = (frame # * frame size) + offset

Paging Arithmetic Laws >>How to convert from logical address to physical address in paging??? Physical address = base address+ offset = (frame # * frame size) + offset   Page size = frame size Logical address space (/size) = 2m Physical address space (/size) = 2x (where x is the number of bits in physical address) Logical address space (/size) = # of pages × page size Physical address space (/size) = # of frames × frame size Page size= frame size= 2n # of pages= 2m-n # of entries (records)in page table = # of pages (# of frames = # of pages) »» »» »» In Inverted paging ONLY

Exercise 8.14 Consider a logical address space of 64 pages of 1024 words each, mapped onto a physical memory of 32 frames. a. How many bits are there in the logical address? b. How many bits are there in the physical address?

Exercise 8.22 Consider a logical address space of 32 pages of 1024 words each, mapped onto a physical memory of 16 frames. a. How many bits are required in the logical address? b. How many bits are required in the physical address?

Exercise 8.19 Assuming a 1-KB page size What are the page numbers and offsets for the following address references (provided as decimal numbers) d. 256 a. 2375 e. 16385 b. 19366 c. 30000

Address Translation Scheme (paging) Address generated by CPU is divided into: Page number (p) – used as an index into a page table which contains base address of each page in physical memory Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit For given logical address space 2m and page size 2n page number page offset p d n m - n

Solution steps (Ex. 8.19) Convert logical address: Decimal Binary Split binary address to 2 parts (page # , Offset) - offset : n digits (where 2n =page size in bytes) - page#: m-n digits) where 2m =size in bytes of logical address space) Convert offset & page# : Binary Decimal

Convert : Decimal Binary 20 21 22 23 24 25 26 27 28 29 210 211 212 213 214 215 1 2 4 8 16 32 64 128 256 512 1024 2048 4,096 8,192 16,384 32,768

Exercise 8.19- solution Page size =2n =1024 B= 210 B # of bits in offset part (n) =10 Offset (decimal) Page # (10 bits) (binary) (6 bits) Logical address 327 2 01 0100 0111 0000 10 0000 1001 0100 0111 2375 934 18 11 1010 0110 0100 10 0100 1011 1010 0110 19366 304 29 01 0011 0000 0111 01 0111 0101 0011 0000 30000 256 01 0000 0000 0000 00 0000 0001 0000 0000 1 16 00 0000 0001 0100 00 0100 0000 0000 0001 16385

Exercise 8.10 Consider a paging system with the page table stored in memory. a. If a memory reference takes 200 nanoseconds, how long does a paged memory reference take? b. If we add TLBs, and 75 percent of all page-table references are found in the TLBs, what is the effective memory reference time? (Assume that finding a page-table entry in the TLBs takes zero time, if the entry is there.)

Effective access time law Effective access time = ∑ [probability of the case × access time of this case] Where (∑ probability of all cases =100%)

Paging Hardware With TLB (fig:8-11)

Exercise 8.8 On a system with paging, a process cannot access memory that it does not own; why? How could the operating system allow access to other memory? Why should it or should it not?

Exercise 8.15 Consider the hierarchical paging scheme used by the VAX architecture. How many memory operations are performed when an user program executes a memory load operation?

Address-Translation Scheme

Two-Level Page-Table Scheme

Exercise 8.6 What is the purpose of paging the page tables?

Exercise 8.18 Consider a computer system with a 32-bit logical address and 4-KB page size . The system supports up to 512MB of physical memory. How many entries are there in each of the following: a. A conventional single-level page table b. An inverted page table

Exercise 8.21 Consider the following segment table: Segment Base Length 0 219 600 1 2300 14 2 90 100 3 1327 580 4 1952 96 What are the physical addresses for the following logical addresses? a. 0,430 b. 1,10 c. 2,500 d. 3,400 e. 4,112 there is a typing error in this row in book

Segmentation >>How to convert from logical address to physical address in segmentation??? IF (offset ≤ limit) then Physical address= base address+ offset Else Trap (address error)

Exercise 8.7 Explain why it is easier to share a reentrant module using segmentation than it is to do so when pure paging is used.

Exercise 8.17 Describe a mechanism by which one segment could belong to the address space of two different processes.

Exercise 8.11 Compare paging with segmentation with respect to the amount of memory required by the address translation structures in order to convert virtual addresses to physical addresses.

Exercise 8.2 Compare the main memory organization schemes of contiguous-memory allocation, pure segmentation, and pure paging with respect to the following issues: a. external fragmentation b. internal fragmentation c. ability to share code across processes

Exercise 8.5 Consider the Intel address translation scheme shown in Figure 8.22. a. Describe all the steps that the Intel 80386 takes in translating a logical address into a physical address. b. What are the advantages to the operating system of hardware that provides such complicated memory translation hardware? c. Are there any disadvantages to this address-translation system? If so, what are they? If not, why is it not used by every manufacturer?

Logical to Physical Address Translation in Pentium

Fig 8-22: Intel Pentium Segmentation

Pentium Paging Architecture