SystemC: Introduction. SystemC  A C++ based class library and design environment for system-level design.  Suitable for functional description that.

Slides:



Advertisements
Similar presentations
Spring Semester 2013 Lecture 5
Advertisements

The C ++ Language BY Shery khan. The C++ Language Bjarne Stroupstrup, the language’s creator C++ was designed to provide Simula’s facilities for program.
COE 405 VHDL Basics Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals Dr. Aiman H. El-Maleh Computer Engineering.
Hardware Description Language (HDL)
High Level Languages: A Comparison By Joel Best. 2 Sources The Challenges of Synthesizing Hardware from C-Like Languages  by Stephen A. Edwards High-Level.
Chapter 6 : Channel Refinement. SystemC Communication Refinement Vital part of overall system refinement: Add more details  To gain more precise analysis.
Sistemas Digitais I LESI - 2º ano Lesson 5 - VHDL U NIVERSIDADE DO M INHO E SCOLA DE E NGENHARIA Prof. João Miguel Fernandes Dept.
Encapsulation by Subprograms and Type Definitions
Why Behavioral Wait statement Signal Timing Examples of Behavioral Descriptions –ROM.
Copyright © 2001 Stephen A. Edwards All rights reserved SystemC Prof. Stephen A. Edwards.
Chapter 5. SystemC 1.0 Main Purpose  Model RTL Instruments  Support diverse data type  Execute concurrently by using METHODs.
Reconfigurable Computing S. Reda, Brown University Reconfigurable Computing (EN2911X, Fall07) Lecture 14: SystemC (2/3) Prof. Sherief Reda Division of.
Reconfigurable Computing S. Reda, Brown University Reconfigurable Computing (EN2911X, Fall07) Lecture 13: SystemC (1/3) Prof. Sherief Reda Division of.
Tasks and Functions Programmable Logic Design (40-493) Fall 2001 Computer Engineering Department Sharif University of Technology Maziar Gudarzi.
OMNET++. Outline Introduction Overview The NED Language Simple Modules.
1 Data Object Object Types A VHDL object consists of one of the following: –Signal, Which represents interconnection wires that connect component instantiation.
From Scenic to SystemC Mehrdad Abutalebi. Outline Introducing Scenic Scenic Implementation Modeling Reactivity A Simple example From Scenic to SystemC.
ECE 2372 Modern Digital System Design
IAY 0600 Digitaalsüsteemide disain Event-Driven Simulation Alexander Sudnitson Tallinn University of Technology.
SystemC Tutorial Author: Silvio Veloso
C#C# Classes & Methods CS3260 Dennis A. Fairclough Version 1.1 Classes & Methods CS3260 Dennis A. Fairclough Version 1.1.
Nirmalya Roy School of Electrical Engineering and Computer Science Washington State University Cpt S 122 – Data Structures Classes: A Deeper Look Part.
Java Classes Appendix C © 2015 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
CS212: Object Oriented Analysis and Design Lecture 6: Friends, Constructor and destructors.
SystemC and Levels of System Abstraction: Part I.
Lecture Set 11 Creating and Using Classes Part B – Class Features – Constructors, Methods, Fields, Properties, Shared Data.
1 Freeha Azmat Saba Zia Dec 02, Agenda Installation Introduction From Verilog to SystemC Counter as an Example Complete SystemC Modeling 2.
1 SystemVerilog Enhancement Requests Daniel Schostak Principal Engineer February 26 th 2010.
Modules and Processes in SystemC A Presentation by: Najmeh Fakhraie Mozhgan Nazarian-Naeini Hardware-Software Codesign Spring 2006.
Winter-Spring 2001Codesign of Embedded Systems1 Reactivity, Ports, and Signals in SystemC Part of HW/SW Codesign of Embedded Systems Course (CE )
1 IMEC / KHBO June 2004 Micro-electronics SystemC Dorine Gevaert.
Winter-Spring 2001Codesign of Embedded Systems1 Introduction to System-Level Modeling in SystemC 2.0 Part of HW/SW Codesign of Embedded Systems Course.
Module 1.2 Introduction to Verilog
Electrical and Computer Engineering University of Cyprus LAB 1: VHDL.
Topics AliasesSubprograms Generics & Configurations.
Ch.2 Part E: VHDL, SystemC EECE **** Embedded System Design.
CprE 588 Embedded Computer Systems Prof. Joseph Zambreno Department of Electrical and Computer Engineering Iowa State University Lecture #10 – Introduction.
UMass Lowell Computer Science Java and Distributed Computing Prof. Karen Daniels Fall, 2000 Lecture 9 Java Fundamentals Objects/ClassesMethods Mon.
 In the java programming language, a keyword is one of 50 reserved words which have a predefined meaning in the language; because of this,
Introduction to Object-Oriented Programming Lesson 2.
04/26/20031 ECE 551: Digital System Design & Synthesis Lecture Set : Introduction to VHDL 12.2: VHDL versus Verilog (Separate File)
VHDL Discussion Subprograms IAY 0600 Digital Systems Design Alexander Sudnitson Tallinn University of Technology 1.
IAY 0600 Digital Systems Design Event-Driven Simulation VHDL Discussion Alexander Sudnitson Tallinn University of Technology.
Chapter 7 Classes and Methods III: Static Methods and Variables Lecture Slides to Accompany An Introduction to Computer Science Using Java (2nd Edition)
Constructor It is a special member of a class that has the following characteristic 1)It has the same name as of its class. 2)It don’t have an explicit.
SystemC Semantics by Actors and Reduction Techniques in Model Checking Marjan Sirjani Formal Methods Lab, ECE Dept. University of Tehran, Iran MoCC 2008.
CIS 4930/6930 System-on-Chip Design Transaction-Level Modeling with SystemC Dr. Hao Zheng Comp. Sci & Eng. U of South Florida.
UMass Lowell Computer Science Java and Distributed Computing Prof. Karen Daniels Fall, 2000 Lecture 10 Java Fundamentals Objects/ClassesMethods.
Object-Oriented Programming Review 1. Object-Oriented Programming Object-Oriented Programming languages vary but generally all support the following features:
1 of 14 Ivan Ukhov Embedded Systems Laboratory Department of Computer and Information Science Linköping University TDDI08: Embedded Systems Design Introduction.
CIS 4930/6930 System-on-Chip Design Introduction to SystemC Hao Zheng Computer Science & Engineering U of South Florida.
Structural style Modular design and hierarchy Part 1
SystemC Language Tutorial Bishnupriya Bhattacharya Cadence Design Systems ISCUG 2013.
Names and Attributes Names are a key programming language feature
Friend Class Friend Class A friend class can access private and protected members of other class in which it is declared as friend. It is sometimes useful.
Java Primer 1: Types, Classes and Operators
2. Specification and Modeling
Structural style Modular design and hierarchy Part 1
Chapter 4: Writing Classes
Tsao, Lin-wei Li, Han-lin Hu, Sun-Bo
Design Flow System Level
SyDEVS Introduction Theory – Paradigm – Implementation
Structural style Modular design and hierarchy Part 1
SYSTEMC.
VHDL Discussion Subprograms
Constructors and destructors
Classes and Objects.
VHDL Discussion Subprograms
Java Programming Language
Introduction to System-Level Modeling in SystemC 2.0
Presentation transcript:

SystemC: Introduction

SystemC  A C++ based class library and design environment for system-level design.  Suitable for functional description that might eventually be implemented as either HW or SW.  Open standard 

Language Architecture C++ Language Standard Core Language Module Ports Processes Events Interfaces Channels Event-driven simulation kernel Data types Bits and bit-vectors Arbitrary precision integers Fixed-point numbers 4-valued logic types, logic-vectors C++ user defined types Elementary Channels Signal, Timer, Mutex, Semaphore, FIFO, etc Channels for MoCs Kahn process networks, SDF, etc Methodology-specific Channels Master/Slave library

Glossary  Module Basic building block for structural partitioning Basic building block for structural partitioning Contains ports, processes, data Contains ports, processes, data Other modules Other modules  Process Basic specification mechanism for functional description Basic specification mechanism for functional description Three types Three types sc_method : sensitive to some ports/signals, no wait statementssc_method : sensitive to some ports/signals, no wait statements sc_thread: sensitive to some ports/signals with wait statementssc_thread: sensitive to some ports/signals with wait statements sc_cthread: sensitive to only clocksc_cthread: sensitive to only clock

Glossary  Interface A set of operations for communication A set of operations for communication No specification about the actual implementation No specification about the actual implementation For example, a signal supports read and write operations For example, a signal supports read and write operations  Port Explicit objects for inter-module communication Explicit objects for inter-module communication Each port object specifies the interface for communication Each port object specifies the interface for communication  Channel An implementation of the interface operations An implementation of the interface operations Performs the actual data transfer Performs the actual data transfer Vary from signals to complex protocols. Vary from signals to complex protocols.

Module  Module is the basic building block in SystemC  SystemC has a macro for convenient module definition Macro name : SC_MODULE Macro name : SC_MODULE Macro implements C++ class inheritance Macro implements C++ class inheritance SC_MODULE(adder) { // ports, processes, internal data }; struct adder: SC_MODULE { // ports, processes, internal data };

Module constructor  Module constructor also defined with another macro Macro name : SC_CTOR Macro name : SC_CTOR SC_CTOR must have module name as an argument SC_CTOR must have module name as an argument SC_MODULE(adder) { // ports, processes, internal data SC_CTOR(adder) { // body of constructor // process declaration, sensitivities etc } };

Module constructor  User can also define own constructor Must include SC_HAS_PROCESS macro to define processes Must include SC_HAS_PROCESS macro to define processes SC_MODULE(adder) { // ports, processes, internal data SC_HAS_PROCESS(adder); adder(sc_module_name name; int other_param): sc_module(name){ // body of constructor // process declaration, sensitivities etc } };

Interface  Consists of a set of operations  Specifies only the signature of an operation name, parameter, return value name, parameter, return value  All SystemC interfaces derived from sc_interface Contains a virtual function called register_port() Contains a virtual function called register_port() Connects a port to a channel through the interfaceConnects a port to a channel through the interface Arguments: port object and type name of the interface that port acceptsArguments: port object and type name of the interface that port accepts

Interface  HW signal interfaces sc_signal_in_if sc_signal_in_if Contains virtual function read()Contains virtual function read() read() returns a constant reference to T such that value may be readread() returns a constant reference to T such that value may be read sc_signal_inout_if sc_signal_inout_if Derived from sc_signal_in_if Derived from sc_signal_in_if Contains virtual function write()Contains virtual function write() write() takes as input a constant reference to Twrite() takes as input a constant reference to T  HW signal interfaces provide the functions that are implemented by channel

Port  Ports provide the well-defined boundaries through which the module interacts Implicit interfaces such a global variable must be avoided Implicit interfaces such a global variable must be avoided  Ports specify the interface that it uses through a template parameter  All ports are derived from sc_port_base class

Port  SystemC provides a template class for creating ports template class sc_port: ……// class derivation details omitted { public : IF* operator->(); // other member functions and member variables };  “IF” denotes the interface class  N is the number of interfaces attached to the port Default value of 1 Default value of 1

Port  Most prominent member of sc_port is operator->() Returns a pointer to the interface Returns a pointer to the interface Any interface method can be invoked through the port Any interface method can be invoked through the port read() and write() below are interface method calls read() and write() below are interface method calls sc_port > p; …… x = p->read(); ….. p->write(y);

Port  User can derive specialized ports from sc_port class Signal ports are provided by SystemC Signal ports are provided by SystemC template class sc_in : public sc_port > …; template class sc_inout : public sc_port > …;

Port and Module SC_MODULE(adder) { sc_in a; sc_in b; sc_out c; // processes, etc SC_CTOR(adder) { // body of constructor // process declaration, sensitivities etc c.initialize(0); } };

Channel  Port and Interface describe the functions available in the communication package  Channel defines the implementation of the communication functions  Channel is derived from the interface It implements the interface if it defines all the interface functions It implements the interface if it defines all the interface functions  More than one Channel might implement that same interface in different ways  A Channel might implement more than one interface

Channel  SystemC provides for Primitive channels Primitive channels Hierarchical channels Hierarchical channels  Primitive channel Examples: sc_signal, sc_mutex, sc_fifo Examples: sc_signal, sc_mutex, sc_fifo  Hierarchical channel User defined channels User defined channels

Channel and Interface template class sc_signal_in_if : virtual public sc_interface { public: // get the value changed event virtual const sc_event& value_changed_event() const = 0; // read current value virtual const T& read const() = 0; }; template class sc_signal_inout_if : virtual public sc_signal_in_if { public: // write the new value virtual void write(const T&) = 0; };

Channel and Interface template class sc_signal :public sc_signal_inout_if, public sc_prim_channel public sc_prim_channel{ public: public: //get the default event virtual const sc_event& default_event() const { return m_value_changed_event;} virtual const sc_event& value_changed_event() const { return m_value_changed_event;} virtual const T& read() const { return m_cur_val;} virtual void write(const T& value_) { m_new_value = value_; m_new_value = value_; if ( ! (m_new_val == m_cur_val)) request_update(); if ( ! (m_new_val == m_cur_val)) request_update();}

Channel and Interface protected: protected: //get the default event virtual void update() { if ( ! (m_new_val == m_cur_value)) { if ( ! (m_new_val == m_cur_value)) { m_cur_value = m_new_value; m_value_changed_event.notify(SC_ZERO_TIME);}} T m_cur_valu; T m_new_val; sc_event m_value_changed_event; };

Channel  Writing process calls write(const &T) method of the channel  write(const &) stores the value in m_new_value Calls request_update() if new value different from previous Calls request_update() if new value different from previous  request_update() informs the SystemC scheduler Change the value of the signal once the current cycle is over. Change the value of the signal once the current cycle is over.  At the end of the simulation cycle Schedule calls update() to change the value of the signal Schedule calls update() to change the value of the signal  update() calls m_value_changed_event.notify() if new value different from current Event notification causes the read process to be resumed in the following simulation cycle Event notification causes the read process to be resumed in the following simulation cycle

Process  Basic unit of functionality in SystemC  Process is contained in a module Described as a member function Described as a member function Not all member functions are processes Not all member functions are processes  Process member function should be registered with the simulation kernel Registration is via a declaration in the module constructor Registration is via a declaration in the module constructor

Process and Module SC_MODULE(adder) { sc_in a; sc_in b; sc_out c; void compute() { c = a + b; } SC_CTOR(adder) { SC_METHOD(compute); sensitive << a << b; c.initialize(0); } };

Process  Two basic kinds of processes SC_METHOD SC_METHOD SC_THREAD SC_THREAD SC_CTHREADSC_CTHREAD  SC_METHOD Always executes its body from beginning to end and returns Always executes its body from beginning to end and returns Does not maintain an implicit execution state Does not maintain an implicit execution state States if required is maintained via module variables States if required is maintained via module variables