W.Skulski Phobos Workshop April /2003 Firmware & software development Digital Pulse Processor DDC-8 (Universal Trigger Module) Wojtek Skulski University.

Slides:

Advertisements

Similar presentations

Xilinx 6.3 Tutorial Integrated Software Environment (ISE) Set up basic environment Select Gates or Modules to Be simulated (Insert Program Code) Run Waveform.

Advertisements

© 2003 Xilinx, Inc. All Rights Reserved Course Wrap Up DSP Design Flow.

Integrated Circuits Laboratory Faculty of Engineering Digital Design Flow Using Mentor Graphics Tools Presented by: Sameh Assem Ibrahim 16-October-2003.

Using an FPGA to Control the Protection of National Security and Sailor Lives at Sea Brenda G. Martinez, Undergraduate Student K.L. Butler-Purry, Ph.D.,

MotoHawk Training Model-Based Design of Embedded Systems.

JET Algorithm Attila Hidvégi. Overview FIO scan in crate environment JET Algorithm –Hardware tests (on JEM 0.2) –Results and problems –Ongoing work on.

1 Performed By: Khaskin Luba Einhorn Raziel Einhorn Raziel Instructor: Rivkin Ina Spring 2004 Spring 2004 Virtex II-Pro Dynamical Test Application Part.

FPGA chips and DSP Algorithms By Emily Fabes. 2 Agenda FPGA Background Reasons to use FPGA’s Advantages and disadvantages of using FPGA’s Sample VHDL.

Software Defined Radio

Wojtek Skulski CERN Oberon Day March /2004 Experiment control and data acquisition using BlackBox Component Builder Wojtek Skulski Department of Physics.

FPGA BASED IMAGE PROCESSING Texas A&M University / Prairie View A&M University Over the past few decades, the improvements from machine language to objected.

SIMULINK Dr. Samir Al-Amer. SIMULINK SIMULINK is a power simulation program that comes with MATLAB Used to simulate wide range of dynamical systems To.

1 Fast Communication for Multi – Core SOPC Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab.

Reconfigurable Computing in the Undergraduate Curriculum Jason D. Bakos Dept. of Computer Science and Engineering University of South Carolina.

v8.2 System Generator Audio Quick Start

Using FPGAs with Embedded Processors for Complete Hardware and Software Systems Jonah Weber May 2, 2006.

GallagherP188/MAPLD20041 Accelerating DSP Algorithms Using FPGAs Sean Gallagher DSP Specialist Xilinx Inc.

FPGA Based Fuzzy Logic Controller for Semi- Active Suspensions Aws Abu-Khudhair.

© 2011 Xilinx, Inc. All Rights Reserved Intro to System Generator This material exempt per Department of Commerce license exception TSU.

© 2011 Xilinx, Inc. All Rights Reserved This material exempt per Department of Commerce license exception TSU Xilinx Tool Flow.

Summer Research Progress: Week 2 – DSP vs FPGA

Delevopment Tools Beyond HDL

General Purpose FIFO on Virtex-6 FPGA ML605 board Students: Oleg Korenev Eugene Reznik Supervisor: Rolf Hilgendorf 1 Semester: spring 2012.

Computer Security Conference 15 APR 2010 FPGAs In The Classroom : Practice and Experience William M. Jones, Ph.D. Department of Computer Science Coastal.

Image Processing for Remote Sensing Matthew E. Nelson Joseph Coleman.

ICMetrics Experimental Platform Jenya Kovalchuk University of Essex 27 January 2012 Ecole Centrale of Lille 1 Part-financed by the European Regional Development.

Model-Based Design and SDR Fabio Ancona Sundance Italia SRL CEO – Sales Director.

Impulse Embedded Processing Video Lab Generate FPGA hardware Generate hardware interfaces HDL files HDL files FPGA bitmap FPGA bitmap C language software.

Trigger design engineering tools. Data flow analysis Data flow analysis through the entire Trigger Processor allow us to refine the optimal architecture.

© 2003 Xilinx, Inc. All Rights Reserved CORE Generator System.

Digital Radio Receiver Amit Mane System Engineer.

1 3-General Purpose Processors: Altera Nios II 2 Altera Nios II processor A 32-bit soft core processor from Altera Comes in three cores: Fast, Standard,

DLS Digital Controller Tony Dobbing Head of Power Supplies Group.

1 of 23 Fouts MAPLD 2005/C117 Synthesis of False Target Radar Images Using a Reconfigurable Computer Dr. Douglas J. Fouts LT Kendrick R. Macklin Daniel.

Concept of Modular Design Module Carriers Embedded or PC-Host Modules A/D,D/A,I/O DSP,FPGA IMAGING,MEMORY Systems Data Acquisition Medical Industrial Control.

© 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only Xilinx Design Flow FPGA Design Flow Workshop.

Xilinx LogiCore Animation and Connect6 game development on Remote FPGA Student - Stephen Conway Supervisor - Fearghal Morgan Co-Supervisor – Martin Glavin.

SW and HW platforms for development of SDR systems SW: Model-Based Design and SDR HW: Concept of Modular Design and Solutions Fabio Ancona Sundance Italia.

Hardware/Software Co-design Design of Hardware/Software Systems A Class Presentation for VLSI Course by : Akbar Sharifi Based on the work presented in.

NIOS II Ethernet Communication Final Presentation

Introduction to FPGA Created & Presented By Ali Masoudi For Advanced Digital Communication Lab (ADC-Lab) At Isfahan University Of technology (IUT) Department.

STATEFLOW AND SIMULINK TO VERILOG COSIMULATION OF SOME EXAMPLES

Preliminary Design of FONT4 Digital ILC Feedback System Hamid Dabiri khah Queen Mary, University of London 30/05/2005.

© 2004 Xilinx, Inc. All Rights Reserved Embedded Processor Design.

1 Implementation in Hardware of Video Processing Algorithm Performed by: Yony Dekell & Tsion Bublil Supervisor : Mike Sumszyk SPRING 2008 High Speed Digital.

Algorithm and Programming Considerations for Embedded Reconfigurable Computers Russell Duren, Associate Professor Engineering And Computer Science Baylor.

W.Skulski APS April/2003 Eight-Channel Digital Pulse Processor And Universal Trigger Module. Wojtek Skulski, Frank Wolfs University of Rochester.

A Monte Carlo Simulation Accelerator using FPGA Devices Final Year project : LHW0304 Ng Kin Fung && Ng Kwok Tung Supervisor : Professor LEONG, Heng Wai.

© 2005 Xilinx, Inc. All Rights Reserved This material exempt per Department of Commerce license exception TSU HDL Co-Simulation.

Tools - Design Manager - Chapter 6 slide 1 Version 1.5 FPGA Tools Training Class Design Manager.

Tools - LogiBLOX - Chapter 5 slide 1 FPGA Tools Course The LogiBLOX GUI and the Core Generator LogiBLOX L BX.

W.Skulski Phobos Workshop April /2003 Digital Pulse Processor DDC-8 (Universal Trigger Module) for PHOBOS. Wojtek Skulski University of Rochester.

© 2003 Xilinx, Inc. All Rights Reserved Course Wrap Up DSP Design Flow.

Graphical Design Environment for a Reconfigurable Processor IAmE Abstract The Field Programmable Processor Array (FPPA) is a new reconfigurable architecture.

Online Muon Capture and Decay Experiment Megan Alexander, Daniel Miner, Wojtek Skulski, Frank Wolfs University of Rochester Work funded by a grant from.

Introduction to Simulink Matlab based Both Continuous Time and Discrete Time Simulation Based on Blocksets Model Based Design: a software model of the.

Introduction to Labs Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee.

1 Level 1 Pre Processor and Interface L1PPI Guido Haefeli L1 Review 14. June 2002.

A commercially available digitization system Fotiou Andreas Andreas Fotiou.

© 2005 Xilinx, Inc. All Rights Reserved This material exempt per Department of Commerce license exception TSU CORE Generator System.

A Brief Introduction to FPGAs

Lynx: A scalable solution utilising FPGAs for high performance data processing Part B: Firmware & Software Development December 2009 CSIR DPSS Presentation.

CoDeveloper Overview Updated February 19, Introducing CoDeveloper™  Targeting hardware/software programmable platforms  Target platforms feature.

The Whole Sort of General Mish Mash Frequently Asked Questions and Trip-ups About the CASPER Libraries and Toolflow Henry Chen, CASPER Workshop, August.

1 Introduction to Engineering Spring 2007 Lecture 18: Digital Tools 2.

Maj Jeffrey Falkinburg Room 2E46E

Integration of OCP and SIMULINK

Production Firmware - status Components TOTFED - status

THE PROCESS OF EMBEDDED SYSTEM DEVELOPMENT

Welcome to MATLAB.

Presentation transcript:

W.Skulski Phobos Workshop April /2003 Firmware & software development Digital Pulse Processor DDC-8 (Universal Trigger Module) Wojtek Skulski University of Rochester

W.Skulski Phobos Workshop April /2003 Outline What tools are available? What needs to be programmed? 1. GUI. 2. Embedded  processor (8051 derivative). 3. Digital signal processing FPGA.

W.Skulski Phobos Workshop April /2003 Software and firmware development tools Entry-level software development. All development tools are free. FPGA: XILINX WebPack ISE. Embedded micro: Keil C compiler, code restricted to 4kB. PC GUI: Shareware edition of BlackBox Component Builder. Expert-level software development. All tools discounted for universities. FPGA. VHDL tools: XILINX ISE, full version. Graphical tools: MatLab and XILINX System Generator. Embedded micro: Keil C compiler, full version. PC GUI: Full edition of BlackBox Component Builder.

W.Skulski Phobos Workshop April /2003 micro processor FPGA Communication with XLM (if using the combo system).

W.Skulski Phobos Workshop April /2003 Programming the GUI GUI development system: BlackBox Component Builder Very robust. No memory leaks. No dangling pointers. Custom graphics. USB interface. Free for education.

W.Skulski Phobos Workshop April /2003 Programming the embedded  processor Embedded micro development system: Keil 8051 C compiler Free intro version. Full version not free (University discount is available). Cypress USB framework. Debugger + monitor available. Has to be done carefully.

W.Skulski Phobos Workshop April /2003 Using FPGAs for Digital Signal Processing What is the advantage of the FPGA over a classic processor? FPGA is highly parallel, hence better performance. Data processing can be pipelined. FPGA becomes an application-specific “custom processor”. More I/O lines than any processor -> wide data paths. What is the disadvantage? More tedious and error prone. Only integer math is supported, no floating point. We know how to program processors, we are learning FPGAs only now. Programming FPGAs has to be done very carefully.

W.Skulski Phobos Workshop April /2003 Programming the FPGA Several design methods. 1. Schematic entry “by hand”. Suitable for small designs. 2. VHDL programming language. Powerful, but tedious. 3. Automatic “core generator”. Precompiled “cores” are instantiated. 4. Graphical LabView-like environment running under MatLab. Design environments. A. Free intro version WebPack, only schematic entry and VHDL are provided. B. Expensive full version ISE XST (University discount is available). Full version = WebPack + Core Generator. C. LabView-like MatLab and Simulink environment from MathWorks, Inc. Programming FPGAs has to be done very carefully.

W.Skulski Phobos Workshop April /2003 Programming the FPGA using schematic FPGA development system: XILINX ISE

W.Skulski Phobos Workshop April /2003 Programming the FPGA in VHDL FPGA development system: XILINX ISE

W.Skulski Phobos Workshop April /2003 Programming the FPGA using Core Generator FPGA development system: XILINX ISE

W.Skulski Phobos Workshop April /2003 FPGA Graphical Design Environment Matlab+Simulink (MathWorks) & System Generator (XILINX) Slide provided by Steve Pauly

W.Skulski Phobos Workshop April /2003 FPGA Graphical Design Methodology Draw block diagram Simulate design Modify diagram Generate VHDL Implement into FPGA Create bit file Program FPGA Slide provided by Steve Pauly

W.Skulski Phobos Workshop April /2003 Pulse can be integrated on the fly Pedestal can be subtracted on the fly Digital pulse processing in the FPGA Baseline-corrected pulse integral available about 400ns after the input pulse, assuming that all three sums are 100ns long. (Why 400? Remember 300ns latency.) t ns

W.Skulski Phobos Workshop April /2003 Signal from a pocket NIM pulser digitized with the DDC-8 at 40 Msamples/s * 10 bits Excellent response to a very fast pulse seen with the “spy channel” Reminder concerning 300ns latency t pulse < t sampling. Digitization made possible by the Nyquist filter f filter = 1/4 f sampling Latency = 300ns. Input pulse t ns

W.Skulski Phobos Workshop April /2003 Summary Three major subsystems to be programmed. Host PC, embedded microprocessor, FPGA. Robust, industrial-grade programming tools. Both the PC and the embedded micro tools are traditional. The integrated compiler, debugger, etc. The FPGA programming is new to us. The promising avenue: graphical FPGA programming. Firmware & software development will take time.