ESD for the Fabless Semiconductor Company Golden Rules of ESD Due Diligence for Third Party Intellectual Property Golden Rules of ESD Due Diligence for Third Party Intellectual Property By Rosario Consiglio, Impulse Semiconductor 2006

Rule #1 It is never too early to make ESD planning is part of your design flow.

Frequent ESD Management Pitfalls Insufficient time is allowed for IP vendors to correct ESD oversights and errors Insufficient time is allowed for IP vendors to correct ESD oversights and errors Checking ESD after package design is frozen (big problem with flip-chip designs) Checking ESD after package design is frozen (big problem with flip-chip designs) Putting off an ESD review until after first silicon reveals a problem Putting off an ESD review until after first silicon reveals a problem Putting off the first ESD review until just days before tape out Putting off the first ESD review until just days before tape out

Frequent ESD Problem Areas Low voltage I/O Low voltage I/O Low voltage PLL blocks Low voltage PLL blocks High speed reference clock blocks High speed reference clock blocks 5 volt tolerant designs on using LV CMOS 5 volt tolerant designs on using LV CMOS All analog IP without specifically designed I/O All analog IP without specifically designed I/O More than three power supply domains More than three power supply domains Power management circuits Power management circuits

Rule #2 The Wafer Foundry will never provide all the ESD support you need.

Rule #2 Comments Wafer Foundry ESD expertise is usually weighted in device design rather than ESD applications Wafer Foundry ESD expertise is usually weighted in device design rather than ESD applications Foundry application guidelines and datasheets only cover 1-2 basic applications (ESD NMOST, PMOST) Foundry application guidelines and datasheets only cover 1-2 basic applications (ESD NMOST, PMOST) Most Layout ESD and latchup rules are only checked manually Most Layout ESD and latchup rules are only checked manually CAD design rule checks, LVS do not include ESD checks CAD design rule checks, LVS do not include ESD checks Ask how the Foundry qualifies IP vendors Ask how the Foundry qualifies IP vendors

Rule # 3 The Integrated ESD level for the whole IC is always less than the sum of its third party IP parts.

Rule #3 Comments IP vendors may try, but cannot anticipate all ESD application problems with their products IP vendors may try, but cannot anticipate all ESD application problems with their products Independent IP providers judge ESD performance of their individual PHY based on their respective test chip results Independent IP providers judge ESD performance of their individual PHY based on their respective test chip results IP vender “A” will not guarantee their ESD circuits will protect IP from vendor “B” IP vender “A” will not guarantee their ESD circuits will protect IP from vendor “B”

Hypothetical IC Layout Example AFE section Vendor A PLL Vendor E CLK SQR Digi tal I/O Ven dor C Digital I/O Vendor B 500 2K2K 4K K Digital SRAM Core Vendor D

ESD Integration Issues Due to required pin combinations, certain ESD discharge paths may be very resistive Due to required pin combinations, certain ESD discharge paths may be very resistive Voltage drops on any particular path may be excessive Voltage drops on any particular path may be excessive ESD clamps from IP vendor “A” may be incompatible with IP from vendor “B” ESD clamps from IP vendor “A” may be incompatible with IP from vendor “B” Insufficient isolation between IP block may result in excessive noise and Latchup Insufficient isolation between IP block may result in excessive noise and Latchup

Important IP ESD Information A test report indicating 2KV HBM, 200V MM, 500V CDM is helpful but insufficient by itself A test report indicating 2KV HBM, 200V MM, 500V CDM is helpful but insufficient by itself Know Pass diode resistance Know Pass diode resistance Knowledge of ESD clamp dynamic resistance or ESD clamping voltage for protection elements Knowledge of ESD clamp dynamic resistance or ESD clamping voltage for protection elements Know I/O cell metal layer composition, and number of squares to compute resistance Know I/O cell metal layer composition, and number of squares to compute resistance Signal buffering/Pi network configuration Signal buffering/Pi network configuration

Possible IC Power Domains 22 sq vdd 32 sq 9 sq 6.1 sq vdd 28 sq vdd 41 sq 28 sq vdd 41 sq 17.5 sq vdd 25.6 sq 2.2 sq vdd3.2 sq 2.2 sq vdd 3.2 sq 9 sq6.1 sq vdd VSS is the outer ring VDD is outer ring VDD I/O I/O clamp M=4 I/O clamp M=2 clamp

Modeling of Core Interconnect May be Necessary for Accurate Estimates

Rule #4 Seek out test data, ask questions.

Test Data From IP Vendors Independent Lab reports for HBM, MM, CDM results. Independent Lab reports for HBM, MM, CDM results. Transmission line pulse I/V for ESD clamps Transmission line pulse I/V for ESD clamps ESD parameters extracted from TLP measurements for wafer foundry processes ESD parameters extracted from TLP measurements for wafer foundry processes Latchup current values for different I/O types over temperature Latchup current values for different I/O types over temperature

IP Provider ESD Design Queries ESD device clamping voltages at 1.5 amps/100ns – is it compatible with wafer foundry ESD limits? ESD device clamping voltages at 1.5 amps/100ns – is it compatible with wafer foundry ESD limits? Noise isolation techniques – is the pass diode voltage drop less than wafer foundry technology limits? Noise isolation techniques – is the pass diode voltage drop less than wafer foundry technology limits? Is the metalization wide enough for low voltage drops? Is the metalization wide enough for low voltage drops?

IP Provider Design Margins Queries continued Are there antenna diodes for internal buffers, supply lines and long signal paths? Are there antenna diodes for internal buffers, supply lines and long signal paths? What analog signals are routed directly to I/O? What analog signals are routed directly to I/O? What is the input Pi network? What is the input Pi network? What foundry data used to design ESD structures? What foundry data used to design ESD structures?

Foundry ESD/latchup parameters Secondary breakdown currents and voltages for ESD layouts Secondary breakdown currents and voltages for ESD layouts Worst case Oxide breakdown statistics Worst case Oxide breakdown statistics Resistor (poly, diffusion) current carrying capacities Resistor (poly, diffusion) current carrying capacities Metalization current carrying capacities Metalization current carrying capacities Via, contact current carrrying capacities Via, contact current carrrying capacities Does the Foundry have data from SEMATECH standard ESD evaluation structures? Does the Foundry have data from SEMATECH standard ESD evaluation structures?

SEMATECH Foundry TLP Benchmarking Structures Courtesy of Sematech