MODERN Final Review ENIAC MODERN Ref. Technical Annex MODERN_PartB Rev2 v3.8 WP1: Giuliana GangemiWP2: André Juge WP3: Wilmar HeuvelmanWP4: Davide Pandini WP5: Loris Vendrame Coordinator: Jan van Gerwen Date: May 3 rd, 2012 Version: 2.0

CONFIDENTIAL MODERN Final Review May 3rd, 2012 Agenda (1) Welcome General information (Jan) –Objectives –Consortium –Amendments –Resources planned and used –Overview of deliverables and milestones status –Dissemination and exploitation –Relationship between workpackages –Other issues, Q&A For WP1 (Giuliana), WP2 (André), WP3 (Wilmar) and WP4 (Davide) –Link with other WPs and Tasks –Progress, highlights and lowlights –Technical status and achievements of deliverables (incl. changes) –Cooperation –Dissemination (publications, patents), exploitation –Other issues, Q&A 2

CONFIDENTIAL Agenda (2) For WP5 (Loris and others) –Deliverables (incl. changes) –Demonstrator goals w.r.t. related project tasks –Major achievements, highlights / lowlights and comparison w.r.t. state of the art –Demo’s and technical highlights: Thales: Philippe Millet / Simon Heywood “License plate detection implementation on FPGA of robust parallel computing architecture ” UNBO / STI: Davide Rossi “Design flow validation for via/metal programmable gate arrays” Tiempo: Marc Renaudin UPC: Francesc Moll Echeto IFXA/IMCA: Michael Fulde LETI: Edith Beigne AMS: Alexander Steinmar –Q&A MODERN Final Review May 3rd,

CONFIDENTIAL MODERN Final Review May 3rd, 2012 Objectives The objective of the MODERN project is to develop new paradigms in integrated circuit design that will enable the manufacturing of reliable, low cost, low EMI, high-yield complex products using unreliable and variable devices. Specifically, the main goals of the project are:  Advanced, yet accurate, models of process variations for nanometre devices, circuits and complex architectures.  Effective methods for evaluating the impact of process variations on manufacturability, design reliability and circuit performance. oReliability, noise, EMC/EMI. oTiming, power and yield.  Design methods and tools to mitigate or tolerate the effects of process variations on those quantities applicable at the device, circuit and architectural levels.  Validation of the modelling and design methods and tools on a variety of silicon demonstrators. Layout and strain induced variability (Synopsys) 4

CONFIDENTIAL MODERN Final Review May 3rd, 2012 Consortium The MODERN Consortium features strong competence and expertise in the field of advanced technologies, with a well-balanced participation between Large Industries, SMEs, Research Centres and Universities from all over Europe. 5

CONFIDENTIAL MODERN Final Review May 3rd, 2012 Amendments 1. The change of project coordinator from ST to NXP and ST-Crolles being replaced by ST- Grenoble 2. The removal of some inconsistencies between some deliverables 3. The subcontracting of work by Glasgow to GSS Ltd. 4. CSEM withdraws due to lack of national funding as of To account for the leaving of some NXP employees and a related change in direction of the NXP PDM group the deliverables D5.3.2 and D5.3.3 are (slightly) changed 6. To account for some technical difficulties encountered in the research activities within ST-I Tasks 3.1, 3.4 and 5.3 are (slightly) changed 7. Change of Deliverables D2.2.6, D2.3.4, D2.2.4, D2.5.3 and correction of text in “ Deliverables list”. 8. Rephrasing of D4.3.4 and changing the relative weight accordingly from WP4 to WP3. 9. The Spanish partner Elastic Clocks S.L. (ELX, partner #4) withdraws from the project due to dissolution of the parent company. 10. Due to a lack of human resources at the Graz University of Technology (TUGI) the contribution of TUGI to Task 5.2 is reduced. 11. In order to facilitate the preparation of the Final Review to move the end date of the project from February 29 th to May 4 th, Partner #6 Infineon Technologies Austria AG is replaced by Intel Mobile Communications Austria due to the takeover by Intel. 6

CONFIDENTIAL MODERN Final Review May 3rd, 2012 Resources planned and used 7

CONFIDENTIAL MODERN Final Review May 3rd, 2012 Overview of deliverables and milestones status (1) Deliverables due >M22 8

CONFIDENTIAL MODERN Final Review May 3rd, 2012 Overview of deliverables and milestones status (1) Deliverables due >M22 9

CONFIDENTIAL MODERN Final Review May 3rd, 2012 Overview of deliverables and milestones status (1) Deliverables due >M22 10

CONFIDENTIAL MODERN Final Review May 3rd, 2012 Overview of deliverables and milestones status (2) Milestones due >M22 11

CONFIDENTIAL MODERN Final Review May 3rd, 2012 Overview of deliverables and milestones status (3) Conclusion: All project Deliverables and Milestones are ready Deliverable D5.2.3: Few partners are waiting for silicon (LETI and TIEMPO 32nm) so their sections contains the characterization plan and the simulated targets rather than the experimental evidence. This will be updated as soon as available D Final Report: Awaiting data from some partners (approval by Legal department) 12

CONFIDENTIAL MODERN Final Review May 3rd, 2012 Dissemination and exploitation MODERN participated in the Poster & Demo Session at European Nanoelectronics Forum 2011 in Dublin, Ireland. Most partners have contributed and attended to the annual European VARI workshops on CMOS Variability On October 6 th and 7 th 2011 the ‘International Workshop on Simulation and Modeling of Memory devices’ was organized in Agrate which was attended by 58 persons. A Workshop at DATE’12 with the theme ‘Variability modelling and mitigation in acurrent and future technologies (VAMM’12)’ was organized. This workshop is a co-operation of the projects ‘Synaptic’, ‘TRAMS’ and MODERN. The public and the internal part of the MODERN web-site are and will be updated regularly.MODERN web-site The publications are listed in the progress reports of the WPs in chapter 3. The actual list of publications with over 103 titles is available from the section ‘papers’ on the MODERN website.section ‘papers’ on the MODERN website 13

CONFIDENTIAL MODERN Final Review May 3rd, 2012 Relationship between workpackages 14

CONFIDENTIAL MODERN Final Review May 3rd, 2012 Other issues Q&A ? 15

CONFIDENTIAL WP1: Target technologies, application domains, design/tool requirements AGENDA Link with other WPs and Tasks Progress, highlights and lowlights Technical status and achievements of deliverables (incl. changes) Cooperation Other issues, Q&A MODERN Final Review May 3rd,

CONFIDENTIAL WP1 Objectives 17 MODERN Final Review May 3rd, Clearly define the issues related to nano-electronic technologies that will be tackled in the MODERN project (e.g. sensitivity of performances, power, yield, deficiencies of existing design techniques, etc). 2. Set the target technologies for which the above listed problems will be faced. 3. Define the specifications of the prototype tools, methods and flows that will come up as solutions of the previously listed problems. 4. Define the requirements of the integration work needed to embed the new tools into the existing design frameworks provided by the EDA partners within the flows in use at ST, NMX, IFX,THL, AMS and NXP. 5. Define up front all activities of all WPs of MODERN exception made of the management. YEAR 3 verify that the requirements specified in D1.1 have been satisfied according what was described in D1.2

CONFIDENTIAL Link with other WPs and Tasks MODERN 2010 Review March 1st,

CONFIDENTIAL Progress, highlights and lowlights 19 MODERN Final Review May 3rd, 2012  The Industrial partners have concluded their work of integration and verification of the tools and methods developed by the MODERN project.  HIGHLIGHT Their conclusion is that the design requirements set up front in Year 1 have been achieved  HIGHLIGHT The flows and tools are working inside the industrial design flows. Lowlight : not all the documentation can be made available but remain available at partners premises

CONFIDENTIAL Progress, highlights and lowlights 20 MODERN Final Review May 3rd, 2012 Note: The technical strategy of NXP has drastically changed since the definition phase of the Modern project. The big investments in large SoC designs in 45 nm have been stopped. Instead the focus of NXP has been in so-called High-Performance Mixed Signal (HPMS) products designed in 65nm and above. Nevertheless in the coming years new product will also use more advanced technologies and products are expected to be designed in 40nm technology. Therefore it is expected that the variation aware timing analysis models and tools developed in WP3.1 and WP3.2 will continue to be very essential in order to cope with the impact of increased variability in the latest deep submicron technologies

CONFIDENTIAL CONCLUSIONS 21 MODERN Final Review May 3rd, 2012  NXP MOR (Model Order Reduction) investigation of Interconnect Networks leads to high speed methods that are used during the design and verification phase of new product designs. Together with the parameterized design methodology for analog blocks these methodologies drastically help to speed up the design (Accelerated IP) and are currently used in production. A noise receiver has been implemented in a production design. Initial results showed unexpected results, unfortunately the current measurement setup cannot provide any insights into the circuit behaviour, but it is expected that future investigations will give a better understanding of noise propagation, shielding and sensitivity for victim circuits.

CONFIDENTIAL CONCLUSIONS 22 MODERN Final Review May 3rd, 2012 AMS The activities based on the WP2 specifications have been successfully fulfilled. The used methodologies and strategies for Tasks T1.2, T2.2, T3.3, T3.4 have been verified by silicon, meet the industrial requirements and are ready to be used for future device development and modelling. ST At the different level of abstraction and in the different design domains we can state that the industrial requirements defined for the tool, methods and models developments inside the MODERN project have been met and the new tools have been integrated in the industrial design flows achieving the targeted objectives.

CONFIDENTIAL CONCLUSIONS 23 MODERN Final Review May 3rd, 2012 IFXA/IMCA Based on the hardware results obtained from WP5 it can be concluded that all requirements and specifications for the monitor & control (M&C) strategies for analog, mixed-signal and & RF circuits have been fulfilled. NMX/Micron The specs and requirements defined within the WP1 activities by NMX/Micron have been successfully achieved and updated; In fact even additional partners involvement and commitment w.r.t. the original DOW have been obtained following the evolution of the outcomes of the first part of the project with excellent results.

CONFIDENTIAL CONCLUSIONS 24 MODERN Final Review May 3rd, 2012 THALES The project is of prime importance to Thales to provide results on many- core processors used for critical systems and developed on process- variability-sensitive technology. As such, Thales succeeded in developing a reliable and predictable parallel architecture, which has the potential to scale with product requirements, by first developing a simulated hardware model and then implementing it on an FPGA, thus demonstrating the feasibility of the approach. While the FPGA implementation did not explicitly address memory or communication faults, it did validate the most important and technically challenging aspect of the work: the ability to reconfigure a chip to tolerate processing node faults.

CONFIDENTIAL CONCLUSIONS 25 MODERN Final Review May 3rd, 2012 WP2WP3 WP4 NXP Matching and 1/f-noise results have been integrated in process blocks and PDK’s. The data we collected, analyzed, and model have been used by the FT/DKD group in NXP- Nijmegen to construct the appropriate process blocks for circuit simulations. Equally important is the fact that we used the results measured on advanced technologies to assess where, when and how future models and process blocks should be modified, refined or expanded. For this we also used the data from other partners  Substrate noise: implementation through guidelines (documentation) and design reviews.  Model Order Reduction: implementation through guidelines, training and supplying a toolbox (plug & play).  EM simulation methodology: implementation through guidelines (documentation) Not involved

CONFIDENTIAL CONCLUSIONS 26 MODERN Final Review May 3rd, 2012 WP2WP3 WP4 AMS  For Task 2.3 an environment has been successfully implemented for generation of correlated statistical SPICE models based on virtual generated statistics  Task T2.2 development, aging modelling of HV transistors including PV, has been done together with TU GRAZ. Implemention of PV aware aging effects as well as development of an appropriate test-chip has been successfully done. Due to personnel changes at TU GRAZ the final verification has not been done.  Matching parameters and also additional analog parameters have been directly implemented in the AMS HiTKIT based on the developments performed in MODERN. Not involved

CONFIDENTIAL CONCLUSIONS 27 MODERN Final Review May 3rd, 2012 WP2WP3 WP4 ST PV aware spice Spice Models have been implemented in the ST-I simulation environment. The models developed confirmed to be “plug and play”, have been used without any integration plan. In month 36 deliverables of WP3 the validation tests have been described T3.1 and T3.2 At the end of the project we have updated ST digital design flow, introducing additional degrees of freedom to maximizing delay sensitivity to FBB keeping the overhead leakage power and area cost as lower as possible while the models created for the Analog IC flow are "plug and play" i.e. do not require integration work  The work done with Thales is fully integrated in ST industrial flow to generate STNoC  All the methodologies developed in T4.2 as part of this task were designed keeping as a strict constraint the easy interoperability with standard RTL-to-GDSII design tools. The proposed methodologies were conceived, designed and verified with the specific aim of being "pluggable" in the existing design flow as an additional, stand-alone extra step that could enhance final performance results without altering the flow in itself.  In T4.4 o Regarding the metal programmable flow, it has been verified that the RTL generated by the is compliant with synthesis tools utilized in ST (e.g. Synopsys design compiler). o Regarding the metal programmable flow, it has been verified that the RTL generated by the flow is compliant with synthesis tools utilized in ST (e.g. Synopsys design compiler) o The “skeleton” layout and schematic containing the not- programmed datapath tiles realized have been verified utilizing a standard design flow. The customization of the skeleton layout and schematic has been automatically performed utilizing a skill (Cadence) script which generates a VIA4 OPUS layer of the specific accelerator implemented starting from the bitstream output of the Griffy front end flow. The skeleton layout and schematic have been further imported in Cadence OPUS and all libraries and views have been exported. See User guide in section 3.1 The whole activity has produced a demonstrator described in WP5

CONFIDENTIAL CONCLUSIONS 28 MODERN Final Review May 3rd, 2012 WP2WP3 WP4 IFX Not involved  Aging model parameters for analog reliability simulator Virtuoso® RelXpert have been extracted and whave been made available as add-on to standard PDKs in design/verification flow.  Results from basic assessment of aging/reliability issues and aging induced PV in key AMS&RF building blocks have been compiled into a comprehensive documentation & catalogue (“impact matrix”) that gives circuit designers guidelines in terms of expected aging impact and strategies how to avoid, minimize or compensate effects accordingly. This documentation is now part of standard verification plans.  In a similar way the developed monitor & control circuit IP portfolio (to enable aging/reliability insensitive analog, mixed- signal and & RF circuits) has been included in the documentation. In addition prototype designs have been made available to the circuit designers Not involved

CONFIDENTIAL CONCLUSIONS 29 MODERN Final Review May 3rd, 2012 WP2WP3 WP4 NMX/ Micron s oftware tools both internal and commercial were improved with respect to PV in terms of models, efficiency, usability ( e.g. allowing to avoid workarounds in handling discrete dopants/traps whitin ‘concentration’ based tools).They didn’t not require any integration work but just an upgrade the version of the tool (e.g. the new release of the SNPS tools described in D5.3.2) The simplified and time saving methodology available in the company were cross-checked against more complete and computationally heavy approaches available in academia to verify (or, if necessary, improve) the coverage of the industrial flow. Results reported in D3.2.2 and D3.2.3 This work were done internally without partners

CONFIDENTIAL CONCLUSIONS 30 MODERN Final Review May 3rd, 2012 WP2WP3 WP4 THL Not involved  The development toolchain used by Thales for application implementation helps us to describe data parallelism as well as the dataflow mechanism in algorithms. In doing so, it maps the application to the target architecture, allowing existing applications to be mapped to the many-core design and compare results.  The principles of the many-core architecture were validated using a SystemC simulator.  An FPGA implementation was developed to demonstrate the feasibility of the technology in the context of a realistic product scenario.

CONFIDENTIAL Technical status and achievements of deliverables (incl. changes) 31 MODERN Final Review May 3rd, 2012  D1.1 Specification of internal design flows,environments and existing tools interfaces and industrial requirements for upgrades  D1.2 Verification of upgrades achieved by the MODERN deliverables according the specifications  D1.3 Integration Specifications  D1.4 Signoff Checks and Documentation, Manuals and User Guides for tools, methods and design techniques released ALL RELEASED

CONFIDENTIAL Collaborations 32 MODERN Final Review May 3rd, 2012  Collaboration have been twofold  With Executive Board, Work Package leaders  With Industrial partners: NMX/Micron, NXP, IFX/Intel, Thales, AMS,ST

CONFIDENTIAL MODERN Final Review May 3rd, 2012 Other issues Q&A ? 33

CONFIDENTIAL WP2 agenda Link with other WPs and Tasks Progress, highlights and lowlights Technical status and achievements of deliverables (incl. changes) Cooperation Dissemination (publications, patents), exploitation Other issues, Q&A 34 MODERN Final Review May 3rd, 2012

CONFIDENTIAL 35 MODERN Final Review May 3rd, 2012

CONFIDENTIAL WP3 Outline Overview & Link with other WPs and Tasks Progress, highlights and lowlights Dissemination (publications, patents), exploitation Cooperation Summary 36 MODERN Final Review May 3rd, 2012

CONFIDENTIAL 37 MODERN Final Review May 3rd, 2012 WP3: Physical/circuit to RT-level Objective –PV-aware and PV-robust circuit design techniques and tools, enabling the design of reliable, low cost, low power, low EMI digital and AMS&RF products Tasks: 1.PV-aware circuit models 2.Methodologies, tools and flows for manufacturability, testability, reliability and yield 3.PV-aware design 4.Design for low noise and EMI/EMC Progress: –The activity is on track, and planned deliverables were delivered –Milestones are on track –A number of scientific publications were published in 2011&2012

CONFIDENTIAL WP3: symbolic synergy 38 MODERN Final Review May 3rd, 2012 T3.1 T3.2 T3.3 T3.4 Symbolic models Statisitical models Etc. ABB techniques Random spice etc. M&C circuits PV-aware design Substrate noise Co- habitation EMI

CONFIDENTIAL WP3: Application overview per task and partner 39 MODERN Final Review May 3rd, 2012 TasksCircuit ModelsMethods Tools&Flows PV aware Circuits EMI/EMC Application DigitalNXP,STI,TUD,TUE, UNRM,LIRM UNBO,NXP,STI, UNCA, UNGL,UNRM POLI,LETI,UPCSTI,LIRM AMSSTI,UNRMNMX,STI,UNRMIFX,UPCNXP,STI RFNXPIFXNXP NVMNMX

CONFIDENTIAL WP3: Domain Overview per Task and Partner 40 MODERN Final Review May 3rd, 2012 T3.1T3.2T3.3T3.4 Digital circuit models TUD, LIRM, NXP, UNRM Statistical methods for digitalLIRM, TUE,TUD Analog circuit modelsSTI,UNRM Timing analysis TUD, TUE, NXP, LIRMM NXP AlgorithmsUNRM,STI Monte CarloUNCA Body BiasUNBO, STI Spice like simulationTUDUNGL, NMX Design methodologies UNBO,NMX,NXP, STI, UNCA, UNGL,UNRM Variability TUD,TUE,NXP, UNRM, STI,LIRM NMX,UNGLIFX EMC/EMINXP,STI Monitor & control for digitalPOLI,UPC,LETI,ST Monitor & control for analogIFX,UPC Regular cellsUPC Substrate NoiseNXP Chip-Package-PCB co-design NXP, ST Software and programming methodsNXP

CONFIDENTIAL WP3: Links with other WPs and Tasks 41 MODERN Final Review May 3rd, 2012 WP2 T2.4 T2.3 WP4 T4.1 T4.2 T5.2T5.3 WP5 T5.1 ST I, UNRM WP3 T3.1 T3.2 T3.3 T3.4 ST I NXP UPC, LETI IFX,LETI, UPC NXP T4.4 UPC T2.5

CONFIDENTIAL Deliverables M36 finalized Highlights: –VARI 2011 conference organized by LIRMM NumberContributorsDeliverable D3.1.3NXP, STI, TUD, TUE, UNRMAutomated and validated characterisation flow for lib cells, and AMS&RF blocks D3.2.3NMX, UNBO, UNRM Integration and validation of high-speed PV-aware simulation tools for digital blocks, AMS&RF blocks, and NVM arrays D3.3.3 IFXA, UPC, POLI Synthesis and simulation of digital blocks, and measurement and verification of critical AMS&RF D3.4.5NXP Design flow for RF co-habitation D3.4.6NXP Measurements of substrate noise monitor D3.4.7ST-I Design solutions for EMI-aware design for automotive, and EMI evaluation of combined IC-package-PCB WP3: Progress, highlights and lowlights 42 MODERN Final Review May 3rd, 2012

CONFIDENTIAL Task T3.1: PV-aware circuit models Progress, high- and lowlights (1) Partners: TUD, LIRM, NXP, ST-I, TUE, UNRM Process variation will be included in existing physical and symbolic circuit models. These models are essential to effectively predict delay variations in order to be able to design reliable and predictable electronic circuits. D3.1.1 NXP, ST-I, TUD, TUE, UNRM (M12) Set of alternative symbolic models for lib cells D3.1.2 LIRM, NXP, ST-I, TUD, TUE, UNRM (M24) Statistical methodology for characterization of digital and AMS&RF circuits D3.1.3 NXP, STI, TUD, TUE, UNRM (M36) Automated and validated characterization flow for lib cells, and AMS&RF blocks 43 MODERN Final Review May 3rd, 2012

CONFIDENTIAL Task T3.1: PV-aware circuit models D3.1.3 Progress, high- and lowlights (2) (TUD/TUE/NXP) Development statistical Spice-level simulator Efficient and accurate statistical models of digital gates at the transistor level to use in the above mentioned simulator (45nm and 32nm technologies), validated against Cadence Spectre Monte Carlo simulations. Suitable, very efficient parameterized statistical wire model to represent interconnect, taking statistical cross-talk into account Statistical methodology for On chip Variation (OCV) –Introduction of tools unknown in semiconductor industry –Ideas from optics and spatial statistics, for determination of OCV –modern ideas from robust statistics for pre-processing 44 MODERN Final Review May 3rd, 2012

CONFIDENTIAL Task T3.1: PV-aware circuit models D3.1.3 Progress, high- and lowlights (3) (UNRM STI) Implementation of additional logic elements in the library Implementation of enhancements in the cell models, particularly in the pin capacitance model. Extension of the verification and validation activity, in both deterministic and Monte Carlo statistical delay prediction. 45 MODERN Final Review May 3rd, 2012

CONFIDENTIAL 46 MODERN Final Review May 3rd, 2012 Partners: UNBO, NMX, NXP, ST-I, UNCA, UNGL, UNRM To compensate for process variation during circuit design the PV-aware circuit models need to be used in new methods for circuit design and future design tools and flows D3.2.1 ST-I, UNBO, UNCA, UNRM (M12) Circuit techniques, and speed-up algorithms for PV-aware circuit simulation D3.2.2 NMX, NXP, UNBO, UNCA, UNGL, UNRM (M24) Standardized PV-aware tools for simulation of digital blocks, AMS&RF blocks, and NVM arrays D3.2.3 NMX, UNBO, UNRM (M36) Integration and validation of high-speed PV-aware simulation tools for digital blocks, AMS&RF blocks, and NVM arrays Task T3.2: Tools and flows for manufacturability, testability, reliability and yield D3.2.3 Progress, high- and lowlights (1)

CONFIDENTIAL Task T3.2: Tools and flows for manufacturability, testability, reliability and yield D3.2.3 Progress, high- and lowlights (2) (UNBO,UNRM,NMX) Adaptive Body Biasing (ABB): –Refined the technique(clustered optimized placement on top of the timing- driven placement ) –System integration –Validation: Mobile SoC system, digital by UNBO, analog by UNRM and NVM from NMX. Yield optimization tooling –Validation on industrial IC (DC-DC converter) –SVM+Optimization(DFL) good results but not at industry level –Netlist+simulator (DF-EPGO) give 40 to 90% Yield enhancement 47 MODERN Final Review May 3rd, 2012

CONFIDENTIAL Task T3.2: Tools and flows for manufacturability, testability, reliability and yield D3.2.3 Progress, high- and lowlights (3) (NMX,UNGL) Sensing circuit activity –Sensitivity analysis and ranking of the most impacting BSIM statistical parameters –Scaling Effective of Variability on Sense Amplifier and its building blocks –Simulations for the whole sense amplifier circuit where the transistor models are generated using the NPM and PCA methods as well as lookup tables of the extracted models Validation on NVM 45nm technology : –methodology is good and accurate –increase in modelling accuracy or scaled devices have been identified 48 MODERN Final Review May 3rd, 2012

CONFIDENTIAL 49 MODERN Final Review May 3rd, 2012 Partners: POLI, IFXA, LETI, UPC Solutions for PV-aware circuit design are proposed by either a monitor & control strategy or by development of low PV sensitive standard cell libraries. Inherently variability robust designs are introduced by restricted design rules, redundant/spare transistors and self-timed logic D3.3.1 CSEM, IFXA, LETI, POLI, UPC (M12) PV-tolerant schematics evaluation and Monitor & Control (M&C) strategies in digital and AMS&RF D3.3.2 CSEM, IFXA, LETI, NXP, POLI, UPC (M24) PV-tolerant lib cell designs and M&C implementation in digital and AMS&RF D3.3.3 IFXA, UPC, POLI (M36) Synthesis and simulation of digital blocks, and measurement and verification of critical AMS&RF Task T3.3: PV-aware design D3.3.3 Progress, high- and lowlights (1)

CONFIDENTIAL Task T3.3: PV-aware design D3.3.3 Progress, high- and lowlights (2) (POLI, IFX) A fully automated design methodology, based on the Measure and Control (M&C) paradigm: –able to improve the timing yield of a system –synthesis of low-power, PV-tolerant digital Ips Circuits techniques to avoid aging in AMS&RF circuits like chopper stabilization can effectively reduce degradation and avoid generation of mismatch M&C concepts work as intended –Burn-in and calibration verified on Silicon –Degradation can be monitored and compensated –DC-DC test-structure is functional, aging cannot be detected 50 MODERN Final Review May 3rd, 2012

CONFIDENTIAL Task T3.3: PV-aware design D3.3.3 Progress, high- and lowlights (3) (UPC,LETI) Regular layout: a new design of the regular fabric VCTA in 40nm technology was completed Tolerant circuits: our proposal of high redundancy logic, called Turtle Logic, has been evaluated at circuit simulation level showing good noise tolerance results Temperature monitoring and control: Two test chips for monitoring some RF blocks were designed and submitted through CMP in ST65nm technology: an inductor-less LNA with temperature monitoring and a tunable VCO Compact PVT sensor IP developed with very low area, a wide dynamic of frequency measurements, an easy integration and a capability to discriminate P, V and T impacts with a minimum set of measurements. 51 MODERN Final Review May 3rd, 2012

CONFIDENTIAL 52 MODERN Final Review May 3rd, 2012 Partners: NXP, LIRM, ST-I Next to process variation there is also a large contribution to the timing variation from EMI/EMC related issues. Additionally, due to miniaturisation and co-habitation of AMS&RF the analogue circuits risks suffering from the digital noise. New design techniques will be proposed to suppress and canalise noise and EMI for improved reliability of the complete electrical system. D3.4.1 LIRM, ST-I: Impact of supply noise, and clock distribution on EMI and circuit timing (M12) D3.4.2 NXP: RF-interaction models for combined PCB-package-IC (M12) D3.4.3 NXP, ST-I: Substrate RF coupling, RF co-simulator, Power Distribution Model (PDN) evaluation and analysis flow for combined IC-package-PCB (M24) D3.4.4 ST-I:Implementation and evaluation of clock tree synthesis techniques for low EMI (M24) D3.4.5 NXP: Design flow for RF co-habitation (M36) D3.4.6 NXP: Measurements of substrate noise monitor (M36) D3.4.7 STI: Design solutions for EMI-aware design for automotive, and EMI evaluation of combined IC-package-PCB (M36) Task T3.4: Design for low noise and EMI/EMC Progress, high- and lowlights(1)

CONFIDENTIAL Task T3.4: Design for low noise and EMI/EMC Progress, high- and lowlights (2) (NXP) Floorplan Methodology based on high level EM/circuit simulation model has been developped D3.4.5 –Model contains: on-chip (domains,padring,sealring,splitter cells, substrate), Package (ground+power pins, bondwires/downbonds, exposed diepad) PCB (ground plane and exposed diepad connections) –Main conclusions: Digital – RxPA main coupling path via exposed diepad + downbonds Downbonds are effective only in combination with a low-ohmic connection exposed diepad to PCB ground Isolation digital – RxPA is not impacted by inter domain spacing, downbonding the sealring, splitter cell cap (<1GHz), domain buffers (<1GHz) Substrate noise sensor: D3.4.6 –First silicon gives no insight –Proposed enhancements: root-cause analysis and FIB develop the sensor with a digital read-out instead of analog output 53 MODERN Final Review May 3rd, 2012

CONFIDENTIAL Task T3.4: Design for low noise and EMI/EMC Progress, high- and lowlights (3) (STI) D3.4.7 EMI simulations flow validated with EMI conducted and radiated emission measurements methodology and design solutions for SSO noise and I/O signals’ conducted EMI analysis and optimization –Validated on automotive industrial microcontroller in CMOSM10 technology –I/Os’ skewing and driving strength reduction are very effective to reduce EMI –Decaps have negligible beneficial impact –Impact of analog IP on EMC: Impact higher than expected even for small IP’s Accurate current signature is mandatory (validated on silicon) 54 MODERN Final Review May 3rd, 2012

CONFIDENTIAL WP3: Dissemination TUD 18 publications (+TUD report and MSc thesis) POLI 2 publications NXP 5 publications STI 10 publications TUE 4 publications UNRM 2 publications UNBO 8 publications UPC 8 publications LIRM 10 publications LETI 2 publications 55 MODERN Final Review May 3rd, 2012

CONFIDENTIAL WP3 cooperation In T3.1 cooperation and common research activities between TUD/TUE/NXP on statistical models and methodologies In T3.1 and T3.2 extensive cooperation between UNRM and STI on In T3.2 strong collaboration between UNBO/UNRM/NMX on integration of techniques for digital, analog and NVM In T3.2 cooperation between NMX and UNGL on test case for compact model with statistical variation In T3.3 successful collaboration between POLI and LETI on topic of PVT monitors In T3.3 strong collaboration between IFXA and UPC on RF circuit monitoring 56 MODERN Final Review May 3rd, 2012

CONFIDENTIAL WP3 Summary Dissemination: extensive list of publications reported Validation –Statistical spice simulator validated with Spectre Monte-Carlo simulations – ABB validated on Mobile_soc design in digital, analog and NVM –Yield optimization tooling validated on Industrial DC-DC converter –Compact statistical model validated on 45nm sensing circuit Demonstrators –Successful demonstration of M&C concepts on testchip –Temperature M&C has been demonstrated on 2 testchips –Compact PVT sensor IP demonstrated –Substrate monitor has been implemented into an industrial design and measurements are done, unfortunately the results are not conclusive yet Cooperation: long list of cooperation between many partners All M24/M36 deliverables completed according to milestones –No major criticality detected/reported by task leaders and partners Successful completion of al WP3 activities 57 MODERN Final Review May 3rd, 2012

CONFIDENTIAL WP4: Outline Link with other WPs and Tasks Progress, highlights and lowlights Technical status and achievements of deliverables (incl. changes) Cooperation Dissemination (publications, patents), exploitation Other issues, Q&A 58 MODERN Final Review May 3rd, 2012

CONFIDENTIAL WP4 Task Structure T4.1: Variability-aware design (LETI, UPC) T4.2: Variation-tolerant, robust, low-noise and low-EMI architectures/micro-architectures (POLI, TMPO, LETI, ST I, TEKL) T4.3: Design of reliable systems (ISD, NMX, ST F) T4.4: Design of regular architectures and circuits for high manufacturability and yield (ST I, TMPO, UPC, UNBO) T4.5: Distributed reconfigurable PV-robust architectures (THL, LIRM) 59 MODERN Final Review May 3rd, 2012

CONFIDENTIAL WP4 Deliverables 60 MODERN Final Review May 3rd, 2012 D4.1.2UPCM30Tape-out of prototype on-chip sensors and level shifter circuits for (self-) adaptive design D4.1.3LETIM36Report on trade-off metrics for (self-) adaptive compensation and optimization techniques D4.2.4TMPOM36Report on PV-tolerant architectures and circuit performance analysis and current profile estimation D4.2.5POLI, ST I, TEKLM36High-level asynchronous synthesis tool and exploitation on high- performance advanced industrial design Advanced power shaping methodology for low-EMI design

CONFIDENTIAL WP4 Deliverables 61 MODERN Final Review May 3rd, 2012 D4.3.4ISD, NMXM36Delivery of a validated macro block of a controller for DLL components DPM controller implementation on the multi-core SoC virtual platform Report on memory architecture to support advanced coding technique for robust NVM design D4.4.3UPCM30Tape-out of a chip based on regular transistor arrays D4.4.4ST I, UNBO, TMPO M36Exploitation of the design flow for signal processing application mapping on the proposed regular architectures, and on customizable IPs Report on regular design impact on yield improvement

CONFIDENTIAL WP4 Domain Overview per Task and Partner 62 MODERN Final Review May 3rd, 2012 T4.1T4.2T4.3T4.4T4.5 Digital IPs/macrosUPC, LETIST I, UNBO Analog/AMS IPs/macrosUPC, LETIISD Asynchronous IPs/macros/cells TMPO, LETITMPO Regular/configurable IPs/fabrics ST I, UPC Architectures/Micro- architectures LETI ISD, ST F, NMXST I, UNBOLIRM Interconnect schemes and on-chip communication LETIISD, ST F CAD flows and integrationTMPO, TEKL, POLIST I VariabilityLETI, UPCTMPO, LETITMPOLIRM EMC/EMITMPO, TEKL, POLI, ST I Reliability/Fault toleranceISD, ST F, NMXTHL Manufacturability and yieldST I,UPC, UNBO, TMPO ReconfigurabilityST F, ISDUNBOLIRM, THL Software and programming methods ST I, UNBOLIRM, THL

CONFIDENTIAL WP4 Technology Overview per Task and Partner 63 MODERN Final Review May 3rd, 2012 TechnologyT4.1T4.2T4.3T4.4T4.5 90nm + eNVMPOLI, ST I, TEKL, 65nmUPCTMPOST F, ISD UPC, ST I, UNBO, TMPO LIRM 45nmLETI 40nmTMPOISDST I, UPC, TMPO 32nmLETI THL NVMNMX

CONFIDENTIAL D4.1.2 Prototype On-Chip Sensors and Level Shifter Circuits for (Self-) Adaptive Design Aggregated the design activities related to on-chip sensors and to adaptive circuits On-chip temperature sensor design in ST 65nm technology submitted in March 2011 Packaged chip received November 2011 Body bias demonstration chip in ST 40nm technology submitted early September 2011, scheduled for Oct. 10th 2011, received late March 2012 Measurements presented in WP5 D MODERN Final Review May 3rd, 2012

CONFIDENTIAL D4.1.2 Prototype On-Chip Sensors and Level Shifter Circuits for (Self-)Adaptive Design Temperature sensor Designed to monitor LNA characteristics in ST 65nm technology Differential temperature measurement with self-calibration capability The test-chip occupies an area of 1mm 2 and features 32 custom- made pads of 75x75  m with a pitch of 100  m 65 MODERN Final Review May 3rd, 2012

CONFIDENTIAL D4.1.2 Prototype On-Chip Sensors and Level Shifter Circuits for (Self-)Adaptive Design Body bias demonstrator Objective: evaluate effectiveness of body bias to reduce variability –Combination of BB with VS (inherent in VCDL circuits) Variability is measured with a VCDL circuit –Statistical deviation of delay measured in the middle of the VCDL chain –Chip with 8 identical copies of VCDL, in regular and non-regular layout styles ST 40nm technology 1.24mm 2 40 digital pads 66 MODERN Final Review May 3rd, 2012

CONFIDENTIAL D4.2.4 PV-Tolerant Architectures and Circuit Performance Analysis and Current Profile Estimation Use of TMPO asynchronous delay-insensitive design technology Consolidated the design flow –Used SDC to drive standard tools –Used placement constraints to guarantee delay insensitivity (i.e. variability tolerance to timing variations) Demonstrated the robustness of TMPO asynchronous design technology –Test-chip designed –Design flow applied –Expected results Collaboration with LETI and ST F 67 MODERN Final Review May 3rd, 2012

CONFIDENTIAL D4.2.4 PV-Tolerant Architectures and Circuit Performance Analysis and Current Profile Estimation Consolidated the design flow Seamless integration into standard flows Use of SDC to: –Cut HS cycles –Constrain timing –Constrain interfaces –Constrain Iso-Forks –Verify timings –Generate SDF Logical simulations with timing Electrical simulations Performance and EMI analysis Timing analysis and verification 68 MODERN Final Review May 3rd, 2012

CONFIDENTIAL D4.2.5 High-Level Asynchronous Synthesis Tool Same SystemC model as synchronous (untimed or with TLM-style handshaking) Asynchronous implementation, with scheduling and sharing SystemC standard language support Lower power (due to explicit control modeling) than desynchronization No clock cycles: –Resources are controlled by handshaking-based control flow –Specification style matches better implementation style than synchronous –Better overall QoR may be possible 69 MODERN Final Review May 3rd, 2012

CONFIDENTIAL D4.2.5 High-Level Asynchronous Synthesis Tool Current status: implemented tool includes –DFG as an input –Petri net construction –State exploration –Schedule pruning optimizations –Support for commutative and associative operations –Optimum scheduling Tested on standard high-level synthesis benchmarks –Comparable results with asynchronous HLS state-of-the-art –Flexible formulation can be easily extended to other cost functions 70 MODERN Final Review May 3rd, 2012

CONFIDENTIAL D4.2.5 Power Shaping For Low-EMI Design Advanced power shaping methodology and design flow for low-EMI design, with integration into mainstream, major vendor, backend tool chains 71 MODERN Final Review May 3rd, 2012 TEKL has integrated its Dynamic Power Shaping™ technology into a Cadence Encounter-based, a Magma Talus-based, as well as a Synopsys ICC- based ASIC backend flow. The flow has been verified independently by tier-1 industry partners, here amongst ST I Seamless integration of the FloorDirector technology into mainstream flows is done by analysing a given design using standard industry formats such as Verilog, SDF and SDC, and exporting modified Verilog as well as flow specific clock tree synthesis directives

CONFIDENTIAL D4.2.5 Power Shaping For Low-EMI Design Results The proposed methodology was applied to an automotive-oriented, multi-processor IC reference design provided by ST I Smooth design flow integration 28% reduction of IC pad current peaks 25% reduction of Max Dynamic Voltage Drop 55% reduction of IC pad voltage fluctuations Up to 30 dBµV reduction of digital core conducted EMI harmonics 72 MODERN Final Review May 3rd, 2012

CONFIDENTIAL D4.3.4 Overview Part I – ISD (two axes of contribution) –Validated macroblock of fault tolerant controller for DLL components –DPM controller implementation on the multicore SoC virtual platform Part II – NMX –Report on memory architecture that supports advanced sensing technique for robust NVM design Part III.a – Recent THL and ST F industrial exploitation (update) –Common FPGA platform of smart camera MPSoC for surveillance, exploiting node reliability (by THL) and an enhanced STNoC providing link redundancy and fault tolerant routing (by ST F) Part III.b – Recent ST F and UNBO collaboration (update) –STNoC technology adopted in the design of a reprogrammable configurable FPGA platform connecting a dynamic number of tiles 73 MODERN Final Review May 3rd, 2012

CONFIDENTIAL D4.3.4 Reliable AMS Blocks Validated SystemC-AMS macroblock of a robust controller using DLL/DPLL components –The block targets clock synchronization for distributed clusters of multicore SoC architectures in the presence of parameter perturbation uncertainties due to process variation –The block models (at behavior-level) specialized circuits for unstable state detection and lock/cycle slip detection –Configuration and performance parameters are time-annotated from equivalent electrical networks at circuit-level –We follow a generic design approach examining open/free tools, device noise and nonlinearities, dynamic PLL disturbance scenarios, operational characteristics and system metrics 74 MODERN Final Review May 3rd, 2012

CONFIDENTIAL D4.3.4 Reliable AMS Blocks DPLL for Clock Synchronization Clock convergence is better for a two-node cluster (left); clock skew rises exponentially with number of cores/cluster. Small frequency variation requires short clock sync interval. In the presence of variations, the transition time between two operating frequencies is increasing quickly with the number of cores (from few cycles to hundreds of cycles) 75 MODERN Final Review May 3rd, 2012

CONFIDENTIAL D4.3.4 Multicore SoC A DPM controller of a multicore SoC VP –The controller explores novel DPM principles on power-manageable components and extends our past AMS work towards reliable and power- efficient multicore SoC –Dynamic frequency scaling (DFS) based on self-adjusting DPLL and clock distribution scheme –By examining related dynamic system metrics, we can explore power- efficiency & reliability tradeoffs, e.g. time/percentage over power budget 76 MODERN Final Review May 3rd, 2012

CONFIDENTIAL D4.3.4 New Sensing Concept Due to the continuous reduction of RWB reading a logic value will actually mean to give the probability to read that logic value A new analog-to-digital sensing circuit has been designed and simulated to associate to every cell his distance from the reference (or references if MLC) Reading error probability will be related to the distance from the reference(s) Sensing operation output will end up in a digital data and a read error probability associated to it through a suitable criteria 77 MODERN Final Review May 3rd, 2012

CONFIDENTIAL D4.3.4 Analog-to-Digital Sensing Architecture Sensing concept is to apply an increasing voltage, like a ramp, to the gate of the reference cell Ramp is stopped when the current on the reference cell is equal to the current in the selected cell. That voltage is then latched and a digital code is generated (analog to digital conversion). Many digital codes are grouped to represent the same digital bit (the number depends on the number of digital bits and the quantization step) A look-up table associates to each digital code a read error probability Simulation results reported in the last deliverable (D4.3.4) 78 MODERN Final Review May 3rd, 2012

CONFIDENTIAL D4.3.4 Industrial Exploitation Collaborative effort on the design/implementation of innovative robust FPGA platform of a smart camera MPSoC (details in MODERN/WP5) The platform connects microblaze processors to STNoC with 16 NI master and 16 NI target (10 ) supporting 32-bit AXI The platform exploits hardware and information redundancy to tolerate transient or repair permanent link, router or processor/memory tile faults STNoC supports link redundancy and source-based fault tolerant routing through runtime network reprogramming of the NI/router routing registers (see D4.3.1, M12 and extensions in D4.3.2, M24) The platform supports fault tolerance through redundant processor cores and innovative task scheduling (see D4.3.2 & D4.5.1, M24) Future extension to packet structure will increase the maximum number of routers that an STNoC packet can go through using source routing 79 MODERN Final Review May 3rd, 2012

CONFIDENTIAL D4.3.4 Cooperations: ST F and UNBO STNoC technology adopted by UNBO in a reprogrammable configurable platform connecting a dynamic number of tiles (details in MODERN/WP4.4). –The platform exploits runtime reprogramming of typical ring-like Spidergon STNoC topology to connect together a dynamic number of tiles –Reprogramming of routing paths enhances both fault tolerance and system performance 80 MODERN Final Review May 3rd, 2012

CONFIDENTIAL D4.4.3 Regular Layout Test Chip Objective: to determine the difference in variability between a fully regular layout (VCTA) and a non-regular conventional layout style Variability is measured on a VCDL circuit, ST 40nm technology Similar design as D4.1.2 without body bias Chip received late March 2012 Measurements presented in WP5 D mm 2 39 digital pads ST 40nm technology Difference between regular and non-regular layout blocks At a cost of a 3X area overhead for VCTA 81 MODERN Final Review May 3rd, 2012

CONFIDENTIAL 82 MODERN Final Review May 3rd, 2012 Function and routing configuration bits set by VIA4 connections ONLY 1 mask customization CMOS065LP, 2 threshold MOS type (LVT-SVT) All tiles identical (complete scalability) ‏ Two 24x16 tiles base macro 1.50 mm 2 base macro area 200MHz target utilization Fully synthesizable logic D4.4.4 Regular Architectures And Programmable IPs gnd vdd Configuration through via connections MT-PiCoGA Layout sight Automatic customization flow Starting from c-lile language

CONFIDENTIAL D4.4.4 Regular Architectures And Programmable IPs 83 MODERN Final Review May 3rd, 2012 CMOS065LP technology Base regular cell with 4 transistors (2xP, 2xN) Active area not continuous Fixed layers up to contacts Customization through M1/M2 connections Save mask cost for different customizations Automatic Customization Flow Pseudo-C DescriptionStandard HDL DescriptionStandard & Automatic Back-End Flow Base cell layout and schematic views

CONFIDENTIAL D4.4.4 ST I Successful Industrial Exploitation SPEAr (Structured Processor Enhanced Architecture), a platform for printers and other peripherals It comprises devices that integrate an advanced core, a central computational cell based on ARM architecture, blocks of peripherals for the USB connection or Ethernet, systems to reduce electromagnetic emissions and above all a reconfigurable logic structure ensuring unsurpassed flexibility in the implementation of highly complex systems 84 MODERN Final Review May 3rd, 2012

CONFIDENTIAL D4.4.4 Customizable Multi-processor Architecture Scalable multi processor cluster composed of 4 main blocks: –On cluster interconnect Based on STNoC –Data storage Multi bank shared memory Global memory –I/O Tile Manages synchronization among cores –Computational tile Handles memory transfers through a DMA Handles hardware accelerated functions through a dedicated accelerators interface Accelerators implemented on a metal programmable area 85 MODERN Final Review May 3rd, 2012 communication and memory architecture Computational tile architecture

CONFIDENTIAL D4.4.4 Programming Model Executions is based on command queues running on an host processor launching: –Parallel kernel execution commands –Memory commands –Synchronization commands Three supported execution models –Data parallel (SIMD) –Task parallel (MIMD) Synchronization is achieved at three level –Commands within a command-queue –Threads within a parallel kernel –Hardware accelerated functions within a thread Three levels of memory hierarchy –Private memory → private to each thread –Local memory s → shared among threads –Global memory → shared among kernels 86 MODERN Final Review May 3rd, 2012 platform model execution models

CONFIDENTIAL D4.4.4 Platform Implementation Technology: ST CMOS065LP Main features: –4 computational tiles –4 customizable datapaths –Two independent clock domains –Global memory: 512Kb –Overall area: 13,5mm 2 –Frequency: 200 MHz (wc com) Computational tile (x4) –Local memory: 8Kb –Private memory: 8Kb DM + 8Kb PM –Buffers: 8x1Kb –Area: 1.25mm 2 Customizable area (x4) –Includes 8 hardware accelerators targeting a motion detection application –Area: 0.1mm 2 87 MODERN Final Review May 3rd, tiles MANYAC platform layout view metal programmable areas computational tile global memory

CONFIDENTIAL D4.4.4 PV-Tolerant Architectures and Delay Insensitivity 88 MODERN Final Review May 3rd, 2012 Same flow as D4.2.4 which produces delay-insensitive logic netlists, plus Iso-forks analysis Use of placement constraints to –Implement Iso-Forks –Avoid timing closure –Ensure delay insensitivity = variability- tolerance –Limit area penalty Maximum size rp group = 27

CONFIDENTIAL D4.4.4 PV-Tolerant Architectures and Delay Insensitivity Demonstrated the benefits of delay insensitivity / variability tolerance At design time –All digital / few asynch cells –Avoid timing closure At chip level –Test-chip tape-out in July 2012 –Waiting for silicon –Board is ready for testing Characterize –Speed-power –Location/Process Cond/ Voltages/Programs 89 MODERN Final Review May 3rd, 2012

CONFIDENTIAL D4.4.4 PV-Tolerant Architectures and Delay Insensitivity TMPO achievements in MODERN WP4 (T4.2 and T4.4) TMPO contribution is to enable the design of variability-tolerant low-EMI asynchronous circuits and evaluate/predict at design time the EMC behavior – Set up a flow to design asynchronous cells and libraries – Set up a flow to estimate timing, current consumption profile and EMI – TMPO demonstrated : Efficiency of its design flow (design time, predictability) : timing, current prediction Efficiency of its design technology to reduce EMI (-20 dB): synch/async comparison Variability tolerance of its design technology and flow w.r.t timings : 32nm test-chip 90 MODERN Final Review May 3rd, 2012

CONFIDENTIAL T4.5 Multicore Architecture And Framework 91 MODERN Final Review May 3rd, 2012 –Find trade-offs in performance, power consumption, reliability, & production costs (small series) for future Thales applications –NIM: protocol translation, frequency adaptation, tile isolation –Supervisor: boot loader, debugger, fault tolerance management –Processor tile: computation units with accelerators and I/O capabilities –SystemC based on OCP TL2 (transaction level) Definition and development of a flexible, highly-parameterized, customizable, user-friendly framework

CONFIDENTIAL T4.5 Fault-Tolerant Scenarios 92 MODERN Final Review May 3rd, 2012 Fault scenarios defined: –tile faults –shared memory faults –network faults –repair strategies T4.5 Time Prediction Spear uses the app. and arch. models to: –produce target C code suitable for datastream applications –run a timed SystemC simulation allowing the user to predict the time spent in a given configuration –to run a functional simulation of the application Time analysis is performed using GTKWave No time prediction during fault-tolerance / repairing mechanisms

CONFIDENTIAL T4.5 Work Done And Results Pedestrian detection application: developed on the multicore architecture using SPEAR_DE General disturbance measurement on the architecture caused by task relocation (memory access performance). –Due to the hypercube structure of the network we expect some low impact on latency and no impact on throughput Measure disturbance caused by task relocation on pedestrian detection performance –Due to the application and mapping, we receive a very low impact from the task migration –The application works as well after the repair process as before 93 MODERN Final Review May 3rd, 2012

CONFIDENTIAL T4.5 LIRM Activities Run-time remapping task for MPSoC Distributed MPSoC architecture (HS scale architecture) from model to hardware Homogeneous architecture strategy Self-adaptive migration tasks Distributed OS developed Monitors (CPU load for instance) used 94 MODERN Final Review May 3rd, 2012 Network layer (packet switching) Hardware processing layer MIPS R3000 MIPS R3000 RAM NI Processor 32 bit type MIPS R3000 CPU No MMU, OS kernel… Simple Interface memory gcc4.0.1 cross-compiler The Network Processor Unit

CONFIDENTIAL T4.5 LIRM Activities 95 MODERN Final Review May 3rd, 2012 Validation System C Model, Architecture Model Exploration (Game theory for instance) Task Migration performances

CONFIDENTIAL T4.5 LIRM Activities Evaluation of a distributed fault handler method for MPSoC Evaluation of dynamic distributed optimization techniques (DFVS, power consumption, variability) –Force directed algorithm –Game theory –Consensus algorithm Fault tolerance mechanisms for MPSoC –Based on “Watch Dog” techniques –Diagnostic, Isolation and recovery techniques Applications driven –Multimedia applications –4G Telecom applications 96 MODERN Final Review May 3rd, 2012

CONFIDENTIAL WP4 Cooperations In T4.3 common research activities and cooperation between ISD and THL In T4.3 collaborative effort on the design/implementation of innovative robust FPGA platform of a smart camera MPSoC (details in MODERN/WP5) between THL and ST F In T4.3 cooperation between ST F and UNBO on STNoC technology adopted by UNBO in a reprogrammable configurable platform In T4.4 cooperation between ST I, UPC, and TMPO on regular design In T4.4 cooperation between ST I and UNBO on a design flow for mapping applications on mask-programmable computational blocks, regular transistor arrays, and via-/metal-programmable datapaths In T4.5 cooperation between LIRM and LETI on fine-grain power optimization under variability In T4.5 cooperation between LIRM and ST F on MPSoC fault tolerance 97 MODERN Final Review May 3rd, 2012

CONFIDENTIAL WP4 Link w/- Other MODERN’s WPs 98 MODERN Final Review May 3rd, 2012 WP3 T3.3 WP4 T4.1 T4.2 T4.3 T4.4 T4.5 WP5 T5.2 T5.3 UPC, LETI LETI, TMPO UPC, TMPO, ST I THL THL, LIRM T3.4 ST I

CONFIDENTIAL WP4 Summary Several WP4 web-meetings to prepare M30/M36 deliverables and the final project review Successful industrial exploitation –ST I SPEAr (Structured Processor Enhanced Architecture), a platform for printers and other peripherals –THL and ST F: design/implementation of innovative robust FPGA platform of a smart camera MPSoC Demonstrators –System MPSoC platform, with task migration, failure analysis, power optimization considering variability effects, and HW implementation of several blocks to propose online optimization – LIRM T4.5 All M30/M36 deliverables completed according to milestones –No major criticality detected/reported by task leaders and partners Successful completion of al WP4 activities 99 MODERN Final Review May 3rd, 2012

CONFIDENTIAL WP5 agenda Deliverables (incl. changes) Demonstrator goals w.r.t. related project tasks Major achievements, highlights / lowlights and comparison w.r.t. state of the art Demo’s and technical highlights: –Thales: Philippe Millet / Simon Heywood “License plate detection implementation on FPGA of robust parallel computing architecture ” –UNBO / STI: Davide Rossi “Design flow validation for via/metal programmable gate arrays” –Tiempo: Marc Renaudin –UPC: Francesc Moll Echeto –IFXA/IMCA: Michael Fulde –LETI: Edith Beigne –AMS: Alexander Steinmar Q&A 100 MODERN Final Review May 3rd, 2012

CONFIDENTIAL DELIVERABLES D5.1.3: TUGI, AMS, NMX, STF2 “PV statistical data analysis coming from standard and improved test structures in different technologies” D5.2.3: TMPO, UPC, NXP, IFXA, LETI, “test chip characterization (evaluation to show effectiveness of PVT circuitry, of basic processing circuits implemented with regular layouts,), calibration of PV robust analysis flows” In Amendment n. 10 TUGI activity has been carved out D5.3.3: ST-I, THL, NXP “Trial PDKs (by ST-I), application programming on robust parallel architectures. Software prototype implementation of parameterized design methodology and MOR for statistical parameter variations” Milestone M5.2 ‘Demonstrator final results’ passed 101 MODERN Final Review May 3rd, 2012

CONFIDENTIAL Demonstrator goals w.r.t. related project tasks Logic CMOS Tech. nodes: 65, 40, 32nm RF / AMS Tech. nodes: 65, 32, 28nm Reliability Aging Noise Performance Robustness Monitoring (T3.3) Redundancy (T3.3) Adaptation (T4.1) Regularity (T4.4) HW & SW Robust architectures (T4.5) HW & SW Monitor & Control (T3.3) 102 MODERN Final Review May 3rd, 2012

CONFIDENTIAL RESULTS T5.1 OWNERNODE (nm) CONTENT Highlights / Lowlights Major achievementsComparison w.r.t. state of the art NMX / Micron NVMCombined mismatch test structures + Works fine - Not tested yet on aggressive CMOS Poly dummy analysisDecoupling among poly CD and implant overlap (*) AMSPowerKelvin RON probe; Matching multiplexer + Functional + Mismatch vs spacing Improved accuracy and repeatability; Ok w.r.t. standard structures, Applied to power devices ST-FLogicKelvin mismatch measurements - Gain measures not clear Accuracy for mean values Trade off: accuracy vs. complex and long e-test 103 MODERN Final Review May 3rd, 2012 (*) L. Bortesi, L. Vendrame, G. Fontana, “Combined test structure for systematic and stochastic Mosfets and gate resistance process variation assessment”, IEEE Conference on Microelectronics Test Structures, March 2010, pp

CONFIDENTIAL RESULTS T OWNERNODE (nm) CONTENT Highlights / Lowlights Major achievementsComparison w.r.t. state of the art IFXA IMCA 32M&C: OPA and VCO + Works as intendedDegradation measured 1st time for 32nm analog and RF building blocks Building blocks are “state-of-the-art” but aging new characterization methods introduced IFXA IMCA 32M&C: SAR-ADC + Works as intendedError correction for aging in ADC proven on silicon Nothing comparable published for ADCs IFXA IMCA 32M&C: burn in, chopping, auto- zeroing + All structures and modes functional; - Autozeroing still in Lab M&C methods proven on silicon Nothing comparable published for analog/mixed-signal IFXA IMCA 28DCDC converter and matching + All structures and modes functional; - no degradation due to hard-failures Digital DCDC in 28nm with good efficiency 1 st DCDC in 28nm TMPO 32Variability Tolerant Asynchronous microcontroller + Design and fabrication of a fully delay insensitive digital sub-system - fabrication delay Robust, variability- tolerant clock-less delay- insensitive circuits and associated CAD flow Unique CAD flow enabling the fabrication of standard cell based delay insensitive circuits 104 MODERN Final Review May 3rd, 2012

CONFIDENTIAL RESULTS T OWNERNODE (nm) CONTENT Highlights / Lowlights Major achievementsComparison w.r.t. state of the art UPC40VCDL with regular structures evaluation of lithography-induced variations using a regular fabric proposal (VCTA). Results confirm a measurable difference in the variability of regular VCTA chains w.r.t. FC Impact of regularity on PV has not been conclusively measured before UPC65LNA with M&CThermal monitoring of RF figures of merit like gain. demonstrated, Novel technique to embed analogue / RF circuits in feedback loops using temperature as observable Novel idea for non- invasive monitoring and healing. Comparison can only be made with electrically invasive techniques. UPC65Adjustable VCO and ILFD - results partially differs from simulations, due to a bug in the EM inductors modelling (underestimation). Operation principle and the optimization trade- offs involving power consumption, tuning and locking ranges of the selected ILFD topology. The measurements did not meet the expected requirements. 105 MODERN Final Review May 3rd, 2012

CONFIDENTIAL RESULTS T OWNERNODE (nm) CONTENT Highlights / Lowlights Major achievementsComparison w.r.t. state of the art LETI32Adaptive Voltage and frequency scaling fine- grain processor cluster Design of a fully dynamically adaptive architecture at fine- grain using other WP developments Full design and verification flow for this mixed-signal complex SoC Compared to existing techniques, fine-grain is the solution to face in-die process variations. THALESFPGARobust parallel computing architecture + multicore on FPGA based on MicroBlaze processors linked with a NoC capable of reconfiguring itself after simulated hardware failure of a core. - simpler application than first targeted. A license plate detection application on a 16-core architecture. 10 cores are actually used, 1 is a supervisor, 5 remain for reconfiguration purposes. After hardware failure of a core, the system reconfigures itself and starts again. Approach of reconfiguring the multicore after failure by doing task migration. Several projects are in this direction like ADAM (French ANR), Recomp (Artemis) or Flextiles (FP7). 106 MODERN Final Review May 3rd, 2012

CONFIDENTIAL RESULTS T OWNERNODE (nm) CONTENT Highlights / Lowlights Major achievementsComparison w.r.t. state of the art NXP65production based test chip for substrate noise modeling verification: Test chip B (CLN65 design) -Measurements didn’t show the expected improvement in digital noise interference, while using “clean” well biasing connections. The root-cause is being investigated Various substrate isolation methodologies implemented on production design NXP140production based test chip for substrate noise modeling verification: (CMOS14) - the first silicon results cannot provide any insights into the circuit behaviour. Substrate noise sensor implemented in production design 107 MODERN Final Review May 3rd, 2012

CONFIDENTIAL RESULTS T5.3 OWNER NODE (nm ) CONTENT Highlights / Lowlights Major achievementsComparison w.r.t. state of the art THALES-SW implementation of the “licence plate detection” Designed at SystemC simulator level Works fine on the FPGA implementation See note in T5.2 ST-I-Trial PDK+ The SVM method used to replace the RSM works fine + Models available and comparable to those generated with old methodology, Tool Model Builder based on SVM works and is fully integrated in ST. Simpler and more linear industrial design flow. More efficient (time and costs) than the previous RSM (see project MANON FP7-PEOPLE- MCA-IAPP ) ST-I-SOC design flow of via/metal programmable gate array functionalVerification successfulFabric usability NXP-Model Order Reduction and parametrized design MORE used by partners (NMX/Micron) Increased automation and usability Steps toward analogue synthesis SNPS-Various implementation (based on IFM and direct statistical method +Implementation of statistical IFM method Results quality verified on same templates with different tools and methods (see T2.2) Enhancement of tool capabilities, performance and usability 108 MODERN Final Review May 3rd, 2012

CONFIDENTIAL …in summary 11 test chips –9 Silicon available (6 confirm the expectations, 3 require additional investigations) –2 waiting for results 1 FPGA successful implementation –HW &SW fully functional –Practical example of a final application 3 SW / flows prototypes and a commercial SW enhancement test structures revised and further improved with a trade-off among test time / accuracy / complexity / silicon area 109 MODERN Final Review May 3rd, 2012

CONFIDENTIAL WP5 Demos and Technical highlights Demo’s and technical highlights: –Thales: Philippe Millet / Simon Heywood “License plate detection implementation on FPGA of robust parallel computing architecture ” –UNBO / STI: Davide Rossi “Design flow validation for via/metal programmable gate arrays” –Tiempo: Marc Renaudin –UPC: Francesc Moll Echeto –IFXA/IMCA Michael Fulde –LETI: Edith Beigne –AMS: Alexander Steinmar 110 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL THALES - DEMO 111 MODERN Final Review May 3rd, 2012

CONFIDENTIAL Thales – DEMO FPGA implementation of vehicle registration plate detection application on robust parallel computing architecture 112 MODERN Final Review May 3rd, 2012 Input Mathematical Morphology Binarise Combine & filter Apply mask Algorithm locates and extracts vehicle registration plate from a larger image

CONFIDENTIAL Multicore architecture 113 MODERN Final Review May 3rd, DDR memory Microblaze processor Memory (BRAM) AXI bus Network interface Node architecture FPGA Console & debug On-chip network Node Router Homogeneous 16-node design Thales NoC 8-bit DIP switches Virtex-6 FPGA DDR memory Console & debug

CONFIDENTIAL Boot process 114 MODERN Final Review May 3rd, 2012 Supervisor node starts first & initialises hardware DDR memory FPGA Console & debug Initialisation code

CONFIDENTIAL Boot process 115 MODERN Final Review May 3rd, 2012 Application binaries read from DDR memory & sent to allocated nodes DDR memory FPGA Console & debug Boot images sent to processing nodes

CONFIDENTIAL Console output – no faults 116 MODERN Final Review May 3rd, 2012 Thales vehicle registration plate detection [ 0] hal_supervisor.c: Booting tile 1 [ 0] hal_supervisor.c: Booting tile 2 [ 0] hal_supervisor.c: Booting tile 5 [ 0] hal_supervisor.c: Booting tile 6 [ 0] hal_supervisor.c: Booting tile 7 [ 0] hal_supervisor.c: Booting tile 8 [ 0] hal_supervisor.c: Booting tile 9 [ 0] hal_supervisor.c: Booting tile 12 [ 0] hal_supervisor.c: Booting tile [ 0] hal_msg.c: Raw packet sent (node=8, type=0, chan=0, r=0, size=19200) [ 8] hal_msg.c: Raw packet received (type=0, chan=0, r=0, size=19200) [ 8] hal_msg.c: Raw packet sent (node=0, type=0, chan=0, r=0, size=19200) [ 0] hal_msg.c: Raw packet received (type=0, chan=0, r=0, size=19200) [ 0] hal_msg.c: Raw packet sent (node=9, type=0, chan=0, r=0, size=19200) [ 9] hal_msg.c: Raw packet received (type=0, chan=0, r=0, size=19200) [ 9] hal_msg.c: Raw packet sent (node=0, type=0, chan=0, r=0, size=19200) [ 0] hal_msg.c: Raw packet received (type=0, chan=0, r=0, size=19200) [ 0] hal_msg.c: Raw packet sent (node=12, type=0, chan=0, r=0, size=19200) [12] hal_msg.c: Raw packet received (type=0, chan=0, r=0, size=19200) [12] hal_msg.c: Raw packet sent (node=0, type=0, chan=0, r=0, size=19200) [ 0] hal_msg.c: Raw packet received (type=0, chan=0, r=0, size=19200) [ 0] hal_msg.c: Raw packet sent (node=13, type=0, chan=0, r=0, size=19200) [13] hal_msg.c: Raw packet received (type=0, chan=0, r=0, size=19200) [13] hal_msg.c: Raw packet sent (node=0, type=0, chan=0, r=0, size=19200) [ 0] hal_msg.c: Raw packet received (type=0, chan=0, r=0, size=19200) [ 0] hal_msg.c: Raw packet sent (node=1, type=0, chan=0, r=0, size=19200) [ 1] hal_msg.c: Raw packet received (type=0, chan=0, r=0, size=19200)... Supervisor starts Application binaries sent to allocated processing nodes NoC messages carrying application data

CONFIDENTIAL Boot process – reconfiguration 117 MODERN Final Review May 3rd, 2012 Supervisor detects a faulty node Chip restarts Reconfiguration manager reallocates task to a spare node DDR memory FPGA Console & debug Faulty node Task reallocated to node 15 Reconfiguration manager

CONFIDENTIAL Console output – node 5 faulty 118 MODERN Final Review May 3rd, 2012 Thales vehicle registration plate detection [ 0] hal_supervisor.c: Tile 5 marked as faulty [ 0] hal_supervisor.c: Using tile 15 as substitute [ 0] hal_supervisor.c: Booting tile 1 [ 0] hal_msg.c: Tile message sent (node=1, type=11, chan=0, r=0, size=8) [ 1] hal_msg.c: Remapped tile 15 as tile 5 [ 0] hal_supervisor.c: Booting tile 2 [ 0] hal_msg.c: Tile message sent (node=2, type=11, chan=0, r=0, size=8) [ 2] hal_msg.c: Remapped tile 15 as tile 5 [ 0] hal_supervisor.c: Booting tile 5 [ 0] hal_msg.c: Tile message sent (node=5, type=11, chan=0, r=0, size=8) [ 5] hal_msg.c: Remapped tile 15 as tile 5 [ 0] hal_supervisor.c: Booting tile 6 [ 0] hal_msg.c: Tile message sent (node=6, type=11, chan=0, r=0, size=8) [ 6] hal_msg.c: Remapped tile 15 as tile 5 [ 0] hal_supervisor.c: Booting tile 7 [ 0] hal_msg.c: Tile message sent (node=7, type=11, chan=0, r=0, size=8) [ 7] hal_msg.c: Remapped tile 15 as tile 5 [ 0] hal_supervisor.c: Booting tile 8 [ 0] hal_msg.c: Tile message sent (node=8, type=11, chan=0, r=0, size=8) [ 8] hal_msg.c: Remapped tile 15 as tile 5 [ 0] hal_supervisor.c: Booting tile 9 [ 0] hal_msg.c: Tile message sent (node=9, type=11, chan=0, r=0, size=8) [ 9] hal_msg.c: Remapped tile 15 as tile 5 [ 0] hal_supervisor.c: Booting tile 12 [ 0] hal_msg.c: Tile message sent (node=12, type=11, chan=0, r=0, size=8) [12] hal_msg.c: Remapped tile 15 as tile 5 [ 0] hal_supervisor.c: Booting tile 13 [ 0] hal_msg.c: Tile message sent (node=13, type=11, chan=0, r=0, size=8) [13] hal_msg.c: Remapped tile 15 as tile 5... [ 0] hal_msg.c: Raw packet sent (node=8, type=0, chan=0, r=0, size=19200) [ 8] hal_msg.c: Raw packet received (type=0, chan=0, r=0, size=19200) [ 8] hal_msg.c: Raw packet sent (node=0, type=0, chan=0, r=0, size=19200) [ 0] hal_msg.c: Raw packet received (type=0, chan=0, r=0, size=19200)... Supervisor starts Faulty tile replaced by spare Other nodes are notified of the reconfiguration as they are booted NoC messages carrying application data

CONFIDENTIAL UNBO ST- I - DEMO 119 MODERN Final Review May 3rd, 2012

CONFIDENTIAL Design flow validation for metal programmable gate array VIDEO: Griffy-C code compilation, VHDL code generation, implementation flow VIDEO: layout view of a customized metal programmable gate array Grammar Check DFG Check Routing-only Detection ILP Extraction Pipeline Management DFG Graph Dump Emulation Model Griffy Netlist Generation Griffy-C Code VHDL code generation Synthesis and P&R Signoff, packaging

CONFIDENTIAL Design flow validation for via programmable gate array VIDEO: Griffy-C code compilation, placement and routing VIDEO: MT-PiCoGA customization flow 121 MODERN Final Review May 3rd, 2012

CONFIDENTIAL MT-DREAM SoC 3.5x3.5 = 12,25 mm 2 cmos065LP 200 MHz wccom target freq. Separate power domains 2 macro Customization:1 Focus on: Macro Instances: Context 0 → ycc2rgb conversion Context 1 → Context 2 → ycc2rgb conversion Context 3 CRC Ethernet FFT 1920 MT-PiCoG4 macro PiCoGA elab. flow structure mapped on FourTunE cells (metal programmable) ‏ test patterns 122 MODERN Final Review May 3rd, 2012

CONFIDENTIAL IFXA/IMCA 123 MODERN Final Review May 3rd, 2012

CONFIDENTIAL IFXA/IMCA: Aging Characterization and Compensation of AMS/RF Building Blocks in 32nm CMOS 124 MODERN Final Review May 3rd, 2012 fast transient effects characterized compensation of aging induced offset model-hardware correlation aging simulation OpAmp VCO

CONFIDENTIAL IFXA/IMCA: 12bit ADC with error correction 12-bit SAR-ADC implemented in 32nm CMOS (planar HKMG) Programmable SAR algorithm: non-binary & binary Typical performance at V DD =1V –f sample =5MS/s, f signal 1.5MHz –I DD =10mA (80% buffer) –ENOB > 10Bit 125 MODERN Final Review May 3rd, um x 138um = 0.026mm2

CONFIDENTIAL IFXA/IMCA: 12bit ADC with error correction Degradation of ENOBs at high f sample due to input buffer –Non-binary search enables error correction and higher sample rate Error correction works also at low sample rates !!! –Non-binary at t0  leakage currents (gate leakage, GIDL, …) –Binary at t0  hysteresis, transient mismatch & leakage currents –Aged: Non-binary search compensates for aging effects 126 MODERN Final Review May 3rd, 2012

CONFIDENTIAL IFXA/IMCA: Digital DCDC in 28nm 1 st integrated digital controlled DCDC in 28nm CMOS Dedicated circuit concepts to deal with reliability in 28nm Promising area scaling and power efficiency achieved Accelerated aging tests prevented by hard-failures due to PCB limitations 127 MODERN Final Review May 3rd, 2012

CONFIDENTIAL UPC 128 MODERN Final Review May 3rd, 2012

CONFIDENTIAL UPC Measurement results for 3 chips –VCO+ILFD with digitally tunable range (65nm) Not conclusive due to mistake in L calculation –Thermal sensor with LNA as CUT (65nm) New self calibrated thermal sensor Demonstration of link between performance and Temperature –Regular vs Full Custom VCDL for PV characterization (40nm) Application of VCTA regular fabric Demonstrated smaller PV in regular circuits Observation of WID and D2D variations 129 MODERN Final Review May 3rd, 2012

CONFIDENTIAL UPC-Thermal sensor Thermal sensor with compensation loop against variations in bias 130 MODERN Final Review May 3rd, 2012

CONFIDENTIAL UPC – LNA thermal sensing Demonstrated correlation between sensor output and electrical characteristics 131 MODERN Final Review May 3rd, 2012

CONFIDENTIAL UPC-Regular layout Initial design had independent power voltage for delay chain and MUX Final chip has tied voltages for delay chain and MUXs Results show that delay chain is the dominant delay in the measurements Measured jitter demonstrates impact of regular layout 132 MODERN Final Review May 3rd, 2012

CONFIDENTIAL UPC- Regular layout results 133 MODERN Final Review May 3rd, 2012

CONFIDENTIAL AMS 134 MODERN Final Review May 3rd, 2012

CONFIDENTIAL AMS technical highlights Ia Novel approach for HV MOS DC monitoring structures –Improved standard Kelvin Structures capable for process monitoring –Standard scribe line can be used –New approach does not need additional area for the additional sense pads –Useable for standard devices & butted devices (VBS=0) 135 MODERN Final Review May 3rd, 2012 a) Standard application for sence /force b) Butted configuration c) Implementation: left new, right standard

CONFIDENTIAL AMS technical highlights Ib - Results Structure is capable for indicating –systematically design errors –Contact difficulties –Generation of process statistics –Accuracy improvement –Significant improvement for high current applications 136 MODERN Final Review May 3rd, 2012 Proven repeatability based on outlier criterion for contact and design errors Performance of sence/force technique vs. non s/f technique over device size relative to standard structure

CONFIDENTIAL AMS technical highlights II On-Chip Multiplexer Mismatch Structures –Support of distance dependent matching –Capable for voltages up to 50V –Capable for currents up to 20mA –Provides gate & drain multiplexing 137 MODERN Final Review May 3rd, 2012 Extracted vth & mobility matching Multiplexer principle Short vs. far distance matching

CONFIDENTIAL LETI 138 MODERN Final Review May 3rd, 2012

CONFIDENTIAL CEA-LETI Demonstrator A fine grain Local Dynamic Adaptive voltage and frequency saling architecture

CONFIDENTIAL Demonstrator Architecture Asynchronous NoC WP4 V/F Local actuators (out of MODERN project) Timing Fault Detectors PVT sensors WP3 4 XP70 µP Dedicated memory blocks Local Controller CVP : Clock- Vraiability-Power

CONFIDENTIAL Power Domains main characteristics Each domain is an independant power and frequency domain : –a GALS scheme within the cluster –domains are synchronous islands using programmable clock generator –Within each domain, the logic core is supplied by Vcore voltage generated from external available voltages : VHigh/VMedium/VLow) –Dynamic variability monitoring using timing fault detection and low area PVT probes Local fine grain power and variability management can be executed during IP computation and communication independently from the others

CONFIDENTIAL Power domain ‘power modes’ (from WP4.1)

CONFIDENTIAL Demonstrator Layout Area: –2784 µm x 1400 µm Technology: –STMicroelectronics CMOS032LP

CONFIDENTIAL Results (from back-end extracted simulations)  For an area overhead of ~10% we can obtain from 20% to 45% energy gain depending on : Intrinsic variability Workload balancing 144 MODERN Final Review May 3rd, 2012

CONFIDENTIAL TIEMPO 145 MODERN Final Review May 3rd, 2012

CONFIDENTIAL TIEMPO Work Demonstrate variability-tolerant circuit design – Delay insensitivity = correct independently of actual delays – Design flow – Test-chip fabrication using STMicroelectronics 32 nm process – Test-chip characterization Collaboration with STMicroelectronics and Leti COPYRIGHT TIEMPO S.A.S – 2012 – Do not copy/forward without prior written approval from TIEMPO 146

CONFIDENTIAL Test-chip Fully asynchronous Fully digital About 500 Kgates Use of a small set of asynchronous cells (13 functions, 50 layouts) compliant with the standard cell library 48 pin QFN package Taped-out in July 2011 Packaged silicon expected beginning of May (delayed) COPYRIGHT TIEMPO S.A.S – 2012 – Do not copy/forward without prior written approval from TIEMPO TAM16 µC RAM GPIO ROM Serial_In/Out RS232 Decoder TIEMPO Test-Chip STMicroelectronics 32nm process 147

CONFIDENTIAL Design flow applied Cells design (coll. Leti) Cells characterization Synthesis using ACC Validation Place and Route (coll. STM) Validation No timing closure Only 2 constraints - Max cap - Max transition Focus on physical verifications ACC synthesis Standard cells Asynch cells P&R SystemVerilog / SDC Verilog SDC / SDF Simulation SystemVerilog Benches Tape-Out Physical verifications COPYRIGHT TIEMPO S.A.S – 2012 – Do not copy/forward without prior written approval from TIEMPO 148

CONFIDENTIAL Test-chip characterization Test-board development – Power supplies, Host interface, PIOs Test programs – Microcontroller BIST – ROM check – RAM read/write test – RS232 test and echo mode – Instruction loops – Loader to execute specific test programs All these test programs provide an output status on the PIOs COPYRIGHT TIEMPO S.A.S – 2012 – Do not copy/forward without prior written approval from TIEMPO 149

CONFIDENTIAL Test-chip characterization COPYRIGHT TIEMPO S.A.S – 2012 – Do not copy/forward without prior written approval from TIEMPO Functionally-guaranteed test chips automatically deliver process-related timing information at their primary outputs Characterization corner 1 Characterization corner 2 Characterization corner 3 Chips should be back early May About 30 packaged circuits, 10 per wafer (slow, typical, fast) Test and characterize speed and power w.r.t –Process conditions –Locations on the wafer –Operating voltages –Test programs Scheduled by mid-June

CONFIDENTIAL Q&A 151 MODERN Final Review May 3rd, 2012

CONFIDENTIAL MODERN Final Review May 3rd,