AT94 Training 2001Slide 1 AT17 Series EEPROM Configuration Memories Atmel Corporation 2325 Orchard Parkway San Jose, CA Hotline (408) OR

AT94 Training 2001Slide 2 architecture behave of CNT6 is signal SQA, SQB : integer range 0 to 6 := 1; begin QA <= To_Vector(3,SQA); VHDL/Verilog Synthesis Schematic Place & Route T pd = 10 ns F max = 100 MHz Size = 12x8 Cells Icc =.2mA/MHz Timing Analysis ATDH2200 ATDH2225 Third Party Programmer Configurator Download Design Entry & Simulation Physical Design (Including synthesis compiler) Board Layout Libraries & Interface Macro Generators Behavioral Program Configuratio n Memory

AT94 Training 2001Slide 3 FPGA/FPSLIC ISP Configuration Memories 65K, 128K, 256K, 512K, 1M, 2M & 4M Serial EEPROMs (Direct Xilinx & Altera OTP Replacement) 7 Sizes –AT17C K Version (8/20 pins) –AT17C K Version (8/20 pins) –AT17C K Version (8/20 pins) –AT17C K Version (8/20 pins) –AT17C Meg Version (8/20 pins) –AT17C Meg Version (20 pins) –AT17C Meg Version (44 pins) Q3/2001 Interface with any Atmel or other SRAM FPGA & FPSLIC - AT6000/AT40K (Atmel FPGA)- OR2/3/4Cxx (ORCA) - AT94K (Atmel FPSLIC)- Altera 1K/6K/8K/10K/20K (Flex) - XC2000/3000/4000/5200- Spartan XCS - Xilinx Vertex XCV- Cypress Delta39K Up to 15 MHz configuration rate Fast, ISP via 2-wire interface 3V (17LV) & 5V (17C) options RECONFIGURABLE! Were #1 in Prog. Were #1 in Prog. Logic ISP memories Configurator SRAM-Based FPGA/FPSLIC - Atmel - Altera - Lucent - Xilinx

AT94 Training 2001Slide 4 ISP 5V or 3.3V Fast programming up to 15MHz Cascade – Multiple devices can be cascaded. Reconfigurable FPGA Memory –EEPROM is priced competitively with OTP products Two Parts in One –AT17Cxxx can also emulate 24Cxxx parts In System (Re)Programmable Easy system hook-up for ISP operation –Can be soldered to PCB - no socket required Key Features and Benefits

AT94 Training 2001Slide 5 Two Parts in One Use ‘spare’ memory like a 24Cxxx device. –Save on cost/Board space/Power consumption. –Use ISP interface mux to enable 2-wire SEEPROM capability AD7 FPGA Configuration memory requirements are stored from zero page to 1AD7 Hex. This memory space is accessed in AT17Cxxx mode by the FPGA (SerEn =1) 1B00 1FFF AT17 Device Address space. ‘Unused’ memory at the end of the AT17Cxxx can be accessed in 24Cxxx mode (SerEn=0). Information such as last number redial/PCI I.D. Plug and Play/IP address etc. can easily be stored or retrieved using a micro-controller. 17CXXX 24CXXX

AT94 Training 2001Slide 6 New Parts / Old Parts Design Differences OSC : Internal Oscillator function available WP : Write Protect, this feature allows portions of the memory to be blocked during Write instructions.

AT94 Training 2001Slide 7 Configurator Availability Atmel & Xilinx Versions AT17C/F series = 2-wire serial ISP AT18F series = JTAG ISP

AT94 Training 2001Slide 8 Configurator Availability Altera Versions AT17C/F series = 2-wire serial ISP AT18F series = JTAG ISP

AT94 Training 2001Slide 9 Simple ISP circuit Use Mux for ISP circuit Figure 1: In-System Programming of AT17C/LV65/128/256 (old) EEPROM in AT40K FPGA Application Figure 2: In-System Programming of AT17C/LV65/128/256 (new) EEPROM in AT40K FPGA Application ISP Programming

AT94 Training 2001Slide 10 ‘A’ Vs ‘Non A’ EEPROM High Density EEPROM AT17(A) Internal oscillator is enabled by default 'A' part is recommended for Altera users Pin out is different Oscillator must be enabled for Altera’s Flex 1K,10K & 6K family, disabled for Altera’s Flex 8K family AT17(Non A) Internal oscillator is disabled by default Non-A part is recommended for Atmel, Xilinx, and Lucent users

AT94 Training 2001Slide 11 Programming Options ATDH2200 board for ISP and stand-alone device programming ATDH2225 for ISP - Recommended for Atmel custom board layout - Allows cascading controlled by software Broad third party programmer support –Faster to program than OTP parts Source Code is available - For development of Microcontrolled programming

AT94 Training 2001Slide 12 ATDH2200E PC Programmer kit for ALL AT17 Series EEPROMs –Standalone programming of Configuration EEPROM, OR –Interface to target board for In-System Programming –Supports.pof,.rbf,.hex,.mcs and.bst file formats Takes files straight from Atmel/Xilinx/Altera/Lucent software –5V and 3.3V operation (from supply or target board) –Choice of 20pin PLCC or SOIC socket adapter ATDH2221 for all 20 pin SOIC ATDH2222 for all 20 pin PLCC (incl. Altera, 2M) ATDH2223 for all 8 pin SOIC ATDH2224 for 44 pin TQFP ATDH2226 for 32 pin TQFP ATDH2227 for 44 pin PLCC –Directly supported by Atmel’s IDS FPGA software CPS (Configurator Programming System) software –Quick start user’s guide NEW!

AT94 Training 2001Slide 13 ATDH2200 Stand-alone Device Programming Parallel Port PC ATDH2200 AT17CXXX Configurator Socket Parallel Cable DB-25M DB-25F

AT94 Training 2001Slide 14 Parallel Port ATDH2200 In-System Programming PC ATDH2200 Target System In-System Programming Connector Header AT17CXXX Configurator In-System Programming Connector Header FPGA Parallel Cable 10-pin Ribbon Cable DB-25M DB-25F

AT94 Training 2001Slide 15 Parallel Port ATDH2225 In-System Programming Cable PC ATDH2225 Target System In-System Programming Connector Header AT17CXXX Configurator FPGA DB-25M NEW! Programming Dongel

AT94 Training 2001Slide 16 CPS Configurator Programming Software AT17 Configurator Programming System s/w Clear and compact GUI Windows 95/98/NT/2000 support 2Meg device support Partitions Altera bitstream files for use in third party programmers Reset polarity verification (on ATDH2200E only) Download data rate calibrated to PC processor Save and restore settings between sessions Enable/Disable internal clock for Altera ‘A’ parts Online help and link to WWW-based FAQ

AT94 Training 2001Slide 17 CF.EXE ( Windows 3.1/95/98 DOS software ) Program from Atmel.bst file format [AT40K] CF /P /I input_file.bst /S code /Z level [/G] [/D LPT1] Program from Altera.pof or.hex file formats CF /A /I input_file.pof /S code /Z level [/D LPT1] CF /A /I input_file.hex /S code /Z level [/D LPT1] Program from Xilinx.mcs file format CF /E /I input_file.mcs /S code /Z level [/D LPT1] Density ‘codes’ are 65, 128, 256, 512, 010 –2Meg part supported in CPS (GUI version of CF) only Reset ‘levels’ are L (active low) or H (active high) Altera file conversion for 3rd party programmers CF /B /I input_file.pof /O output_file.bst /F HEX CF /B /I input_file.hex /O output_file.bst /F HEX Source code for CF available on request (cf.c)

AT94 Training 2001Slide 18 AT40K Configuration Statistics DeviceConfiguration Bits*Configurator AT40K0563KAT17C/LV65 AT40K10135KAT17C/LV256 AT40K20236KAT17C/LV256 AT40K40521KAT17C/LV512 AT40K80916KAT17C/LV010 AT40K KAT17C/LV020 Configurator AT40K * = Can be reduced by using bit-stream compression option

AT94 Training 2001Slide 19 FPSLIC Configuration Statistics DeviceConfiguration Bits* Configurator* AT94K10423KAT17LV512 AT94K20524KAT17LV010 AT94K40809KAT17LV010 Configurator AT94K * = Can be reduced by using bit-stream compression option

AT94 Training 2001Slide 20 Drop-In of AT17C65/128/256 AT40K FPGA Application

AT94 Training 2001Slide 21 ISP of AT17C/LV65/128/256(Old Vs New) EEPROM New (No Multiplexor)Old (using Multiplexor)

AT94 Training 2001Slide 22 Drop-In of AT17C512/010/002 AT40K FPGA Application

AT94 Training 2001Slide 23 In-System Programming of the AT17C/LV512/010/002 AT40K FPGA Application

AT94 Training 2001Slide 24 ISP of New Low Density(AT17C/LV65/128/256) VS High Density(AT17C/LV512/010/002)

AT94 Training 2001Slide 25 Drop-In of AT17C65/128/256 AT60xx FPGA Application

AT94 Training 2001Slide 26 In-System Programming of the AT17C65/128/256 (Old) RESET/OE Programming Arrangement AT60xx FPGA Application Old Version

AT94 Training 2001Slide 27 In-System Programming of the AT17C65/128/256 (New) RESET/OE Programming Arrangement AT60xx FPGA Application Note : Reset Polarity of the EEPROM is programmed HIGH for AT6K devices New Version

AT94 Training 2001Slide 28 Drop-In Replacement of XC17/AT17 PROMs Xilinx/Lucent FPGA Application

AT94 Training 2001Slide 29 In-System Programming of the AT17C65/128/256 RESET/OE Programming Arrangement Xilinx/Lucent FPGA Application

AT94 Training 2001Slide 30 In-System Programming of the AT17C512/010/002 Xilinx/Lucent FPGA Application

AT94 Training 2001Slide 31 In-System Programming of the AT17C512/010/002 Cascaded Arrangement Xilinx/Lucent FPGA Application

AT94 Training 2001Slide 32 In-System Programming of the AT17C/LV020 Xilinx/Lucent FPGA Application

AT94 Training 2001Slide 33 Drop-In Replacement of the EPC1064/EPC1213 External Oscillator Arrangement Altera FPGA Application

AT94 Training 2001Slide 34 In-System Programming of Old Low Density(AT17C/LV65A/128A/256A) VS New Low Density(AT17C/LV65A/128A/256A) using Altera FPGA New (No Multiplexor)Old (using Multiplexor)

AT94 Training 2001Slide 35 Drop-In Replacement of the EPC1064/EPC1213 Altera FPGA Application

AT94 Training 2001Slide 36 Drop-In Replacement of the EPC1441/EPC1/EPC2 Internal Oscillator Arrangement Altera FPGA Application

AT94 Training 2001Slide 37 Drop-In Replacement of the EPC1441/EPC1/EPC2 Internal Oscillator and Cascaded Arrangemen Altera FPGA Application

AT94 Training 2001Slide 38 In-System Programming of the AT17C65(A)/128(A)/256(A) RESET/OE Programming Arrangement Altera FPGA Application

AT94 Training 2001Slide 39 In-System Programming of the AT17C65A/128A/256A(older version) RESET/OE Programming with External Oscillator Arrangement Altera FPGA Application

AT94 Training 2001Slide 40 In-System Programming of the AT17C512A/010A/002A Altera FPGA Application

AT94 Training 2001Slide 41 In-System Programming of the AT17C512A/010/002A Internal Oscillator Arrangement Altera FPGA Application

AT94 Training 2001Slide 42 In-System Programming of the AT17C512A/010A/002A Internal Oscillator and Cascaded Arrangement Altera FPGA Application

AT94 Training 2001Slide 43 In-System Programming of the AT17C512A/010A/002A External Oscillator Arrangement Altera FPGA Application

AT94 Training 2001Slide 44 In-System Programming of the AT17C/LV020A Internal Oscillator Arrangement Altera FPGA Application