OCIECE Winter 2002 High-Speed Low-power VLSI New Single-Clock CMOS Latches and FlipFlips with improved Speed and Power [2] & A New True-Single-Phase-Clocked Double-Edge-Triggered Flip-Flop for Low-Power VLSI Designs [7] A New True-Single-Phase-Clocked Double-Edge-Triggered Flip-Flop for Low-Power VLSI Designs [7]

Discussion States Introduction. Motivation for TSPC and DET Flip-Flops. New techniques for high-speed TSPC and single clocked Flip- Flops and latches. A New technique for TSPC Dual-edge-clocked Flip-Flop. A new approach for Power Consumption comparative analysis of Single Edge Triggered /Dual Edge Triggered Flip-Flops. Results and comparisons Conclusions Questions

Static vs. Dynamic Latches A Static Latch: A cross-coupled inverter pair produces a bistable element. The bistable states are used to memorize binary data as long as the supply voltage exists [10].bistable Another signal(s) (Clock) is/are used to allow transparency or no- transparency between the I/P and O/P of the bistable element. A Dynamic Latch: Temporary storage of a charge in the parasitic capacitors of a circuit that is periodically refreshed. The stored charge is used to memorize binary data [10]. A Clock signal is used to allow transparency, partial transparency or no-transparency between the I/P and O/P of the circuit. DQ Clk

Static, Semi-static and Dynamic Flip-Flops Static (Non-precharged) Flip-Flop: a cascaded pair of static latches clocked in a complementary style. D Clk Q Semistatic Flip-Flop: a cascaded pair of static and dynamic latches clocked in a complementary style. Fully dynamic Flip-Flop: a cascaded pair of dynamic latches clocked in a complementary style. Differential Flip-Flop: a cascaded pair of a static, dynamic or mix of differential latches clocked in a complementary style. It deals with differential inputs and outputs. D Clk Q DQ

Total power consumption of the clocking system (Pck) can be expressed as: P ck = P ckgen + P gw + P lw + P g + P reg = ( 1 + 1/ k + 1/k /k n ). V s 2. f. [ C j + C gw + C lw + C g ] + P reg (eqn 1) where, P gw : Power consumption of global wiring capacitances P lw : Power consumption of local wiring capacitances P g : Power consumption due to total clocked gate capacitance P reg : Power consumption in the flip-flops, k : Tapering factor of the clock generator (clock buffer) C g : Total gate capacitance of clocked transistors of the clocking system, and C j : junction cap. of the source-drain regions of the output node of the clock generator Data Ckint D C Q F/F CL1 D C Q F/F Clw.1 Ckext Clock Generator Cg.1 Cj D C Q F/F CLn D C Q F/F Clw.n Cgw Cg.n Power Consumption in the Clocking System of a Synchronous Pipelined circuit

P ck = V s 2. f. [C j + C gw + C lw + m. C gf ] + m. P gf (eqn 2) where m : total number of flip-flops in the clocking system C gf : Total clocked gate capacitance per flip-flop P gf : Power consumption of one frequency f Therefore, the power consumption of the clocking system can be minimized by: 1. Reducing C gw and C lw E.g. Using True Single Phase clocking techniques (TSPC). 2. Reducing the number of clocked transistors per flip-flop ( C gf term) E.g. Using Single Transistor Clocked FF (STC). 3. Utilizing the two edges of the clock e.g. (Dual Edge Triggered FF). 4. Using minimum transistor size, and careful layout design to reduce P gf.

TSPC Basic stages Basic (non-differential) TSPC Edge triggered FF are : Pre-charged version (dynamic) PP+SP+PN+SN Non-pre-charged (static) SP+SP+SN+SN Low power bottlenecks: 1. clocked transistors with   Pre-charged nodes with  Speed bottlenecks : P-blocks to provide complementary inputs to n- blocks. (2 stages +Inv.) delay PP   PN   SP  SN 

Precharged Single stage TSPC Full-latch Advantages: 1- High and low input total latching. 2- Isolated output node. (Infinite impedance). 3- The precharge state is not showing on the O/P at the start of the evaluation. 4- No need for a stable input. NMOS transistor sizing is important in order not to load the pre-charged node. (PN + SN) + FL(P) + INV   In   D D (PN/SN) + FL(P) + INV   In   D D

Nonprecharged Single stage TSPC Full- latch (PSN+SN) + FL(P) + INV   In   D D * PSLT(N) + FL(P) + INV  D D  In  * N-latch to become PSN. Charge sharing compensation. Only 3 clocked transistors in the PSLT. Essential need for a stable input.

Non-Differential semistatic flip-flops Simplified version Conflict-free Full latch Transistors in the dotted box should be kept to a minimum size to minimize the load. PN + SN + SFL(P) + INV

DSTC1(P) DSTC1(N)  Out In CVSL and Single-Transistor-Clocked TSPC dynamic and static differential latches SSTC1(P) SSTC1(N) p-latch n-latch Availability of complementary outputs. STC charge sharing problems Can Not be recovered in DSTC1. Can be recovered in SSTC1. In  Out In * * Out In Out  * * In  Out In Out  In  Out   In Ou t In

High speed differential Flip-Flops SP  In SP * * * In SSTC1(N)  * * *  D D Semistatic Flip-Flop ( (SP + SP) + SSTC1(N) ) Dynamic Flip-Flop ( (SP + SP) + DSTC1(N) ) In DSTC1(N) SP   * * * * * * In  D D An opportunity to remove the speed bottleneck using the following principle; “The master does not have to be a full-latch and it is enough to have only one isolated output state as long as it is identical to the nontransparent input state of the slave.” [2]

DSTC2(P) In  * * * * DSTC1(N) D  D D In   * * * * * *  D A high-speed dynamic differential Flip-Flop (cont’d) P-block is too fast, so n-transistors need to be minimized to give enough setup time. SP stages are merged to remove more P-transistors. A correspondence showed an input glitch related problem leads to a poor logic-level zero output. Capacitive coupling (x-D). Charge sharing (bj - D) Positive edge-triggered dynamic ( (SP + SP) + DSTC1(N) ) xx bj

DSTC1(N)DSTC2(P)  * * * * InIn In  D D Only used for p-termination of a pipeline Whenever a pipeline is ended with a DSTC2(p), a termination stage is needed to fully latch the output [2]. A high-speed dynamic differential Flip-Flop (cont’d)

 SSTC1(N) * * SSTC2(P) In  * * * * ** D D A high-speed fully static differential Flip-Flop DSTC2 p-latch to be converted to SSTC2(P): A minimum inverter and two minimum n-transistors to low output from floating to high.

Performance Comparison [2]

Conventional Dual Edge Triggered (DET) Flip-Flops D    Q Fig 3  

A new TSPC Dual Edge Triggered (DET) Flip-Flop The TSPC DET leads to less Pw. Less number of clocked transistors => less Cgf Less number of speed bottleneck devices. No PP/PN stages leads to less activity in the internal nodes.

Dual Edge Triggered (DET) Flip-Flop Speed calculations Setup time: tsu = max (tsu1 + tsu2) Clk-to-output delay: tcq = max (tcq1 + tcq2) The speed figure of the DET FF:  tsu + tcq Max. toggle frequency of the DETFF = 1 / (2 * speed figure) = 500MHz CL D C Q DEFTFF D C Q Data Clock tsu1 tsu2 tcq2 Clock Data Q

Power consumption in the clocking system associated with a SET/DET Flip-Flops P gf ( power consumption per frequency f ) = C ff.V dd 2. f..... (eqn 3) where, C ff = Equivalent capacitance of one flip-flop, P ck = V s 2. f. [ C j + C gw + C lw + m. C gf ] + m. C ff. V dd 2. f = V dd 2. f ( C clk + C reg ), assuming for V s = V dd = V dd 2. f. C tot A pipelined FIR macro (No. of FF’s = 2616) was implemented and a comparative analysis was done showing a power reduction of 36% compared to the SETFF implementation.

A new approach for Power Consumption analysis of SET/DET Flip-Flops [5] In the absence of Glitches; C j = the node capacitance.  j = transition node j D Clk Q D D Q Q 1 0 Z Y Power consumption of the clock nodes Clk DQ D QQ X For equal data rate,

A new approach for Power Consumption analysis of SET/DET Flip-Flops [5] Input Glitch Analysis: where,  average transitions between two active clock edges. Per one glitch transistion. Where, Per one glitch transition. D Clk Q D D Q Q 1 0 Z Y Q D D QQ X

Conclusions [2],[7] DET flip-flops is more sensitive to signal glitches wrt SET FF. In case of applications that have low transistion probability of the input signals and reduced glitching, the power savings using DET instead of SET can be significant. (Up to 36%) according to the new proposed TSPC FF. The proposed DETFF has a very challenging power-delay product performance. [12] With the trend of increasing Clock frequency, it will be increasingly difficult to control both edges of the clock in the clock distribution system. SSTC1, SSTC2, DSTC1, DSTC2 based Flip-flops showed superior improvement in delays by factors of 2.2 and 2.4 in the Semistatic and fully static styles resp. PDP reduced by factors of 3.4 and 6.5 for (  in the Semistatic and fully static styles resp.

Conclusions [2],[7] New proposed high-speed flip-flops with logic related transistors are purely n-type in both n-latches and p-latches which gives the speed advantage to this approach in designing flip-flops.

[1] J. Yuan and C. Svensson, “High-Speed CMOS Circuit Technique,” IEEE J. Solid-State Circuits, vol. 24, no.1, pp.62-70, Feb [2] J. Yuan and C. Svensson, “New Single-Clock CMOS Latches and Flipflops with Improved Speed and Power Savings,” IEEE J. Solid-State Circuits, vol. 32, no.1, pp.62-69, Jan [3] W. M. Chung and M. Sachdev, “A Comparative Analysis of Dual Edge Triggered Flip-Flops,” [4] R.P. Llopis and M. Sachdev, “Low Power, Testable Dual Edge Triggered FlipFlops”, International on Low Power Electronics and Design, 1996, pp [5] A.G.M. Strollo, E. Napoli, and C. Cimino, “Analysis of Power Dissipation in Double Edge-Triggered Flip-Flops,” IEE Trans. On VLSI Systems, Vol. 8, no.5, Oct [6] S.M.M. Mishra, S.S.Rofail and K.S.Yeo, “Design of High Performance Double Edge-Triggered Flip-Flops,” IEEE Proc. Circuits Devices Syst., Vol.147, no.5, Oct References

[7] J.S.Wang, “A New True-Single-Phase-Clocked Double-Edge-Triggered Flip-Flop for Low-Power VLSI Designs,” IEE Int’l Symposium on Circuits and Systems, pp June 9-12, [8] G.M.Blair, Comments on “New Single-Clock CMOS Latches and Flip-flops with Improved Speed and Power Savings,” IEEE J. Solid-State Circuits, vol.. 32, no.10, pp , Oct [9] V.Stojanovic and V.G.Oklobdzija, “Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems,” IEEE J. Solid-State Circuits, vol.. 34, no.4, pp , April [10] M.Afghani and J. Yuan, “Double-edged-triggered D-Flip-Flops for high speed CMOS circuits,” IEEE J. Solid-State Circuits, vol.SC-26, no.8, pp , Aug [11] Jan N. Rabaey, “Digital Integerated Circuits: A Design Perspective”, 1996 References

Questions?

The Bistability principle [10] The width of the trigger pulse needs to be larger than the total propagation delay around the circuit loop. [10]