DELAY INSERTION METHOD IN CLOCK SKEW SCHEDULING BARIS TASKIN and IVAN S. KOURTEV ISPD 2005 High Performance Integrated Circuit Design Lab. Department of Electrical and Computer Engineering

Outline Background and Motivation Topological Limitations on CSS Experimental Results Conclusions

Introduction High-Performance IC Clock skew scheduling Target: Minimum clock period Observe limitations –Theoretically

Research Objective Objective: Improve the efficiency and results of clock skew scheduling through systematic delay insertion Reconvergent paths Edge-sensitive circuits Level-sensitive circuits

Local data path Circuit graph System Modeling

Timing Parameters

Flip-Flop Operation Positive edge-triggered

Latch Operation Positive level-sensitive

Time Borrowing Flip-Flop basedLatch based T FF = D P 12 T L  D P 12 =T FF

Clock Skew T skew (i,f) = t i - t f Clock signal delay at the initial register Clock signal delay at the final register

Clock Skew Scheduling CIRCUIT TOPOLOGY CLOCKING METHODOLOGY MAX OP. FREQUENCY TIMING SCHEDULE CLOCKING SCHEDULE SENSITIVITY * INPUT OUTPUT

CSS: Edge-Sensitive Zero clock skew Non-zero clock skew T FF = D P 12 T FF skewed  D P 12 =T FF

Edge-Sensitive CSS Model Linear Programming (LP) model 1: J. P. Fishburn, Clock Skew Optimization, IEEE Transactions on Computers, Vol C-39, pp , July

CSS for Level-Sensitive Flip-flop-based Zero clock skew Latch-based Non-zero clock skew T FF = D P 12 T L skewed  T L  D P 12 =T FF

Level-Sensitive CSS Model Linear Programming (LP) model 1: B. Taskin and I.S. Kourtev, Linearization of the Timing Analysis and Optimization Level-Sensitive Digital Synchronous Circuits, IEEE Transactions on VLSI, Vol 12, No 1, pp , January

CSS Topological Limitations Series of data paths –Small practical limitations on CSS Data path cycles –Limit minimum clock period Reconvergent paths –Unexplored –They do matter!

Linear Topology Series of local data paths Small practical limits for clock skew scheduling

Linear Topology Timing 1

Linear Topology Timing 2

Data Path Cycles Defined for retiming Limiting for clock skew scheduling

Data Path Cycles Timing

Reconvergent Paths Common topology Lower bound T min

Reconvergent Paths Timing

Delay Insertion Add delays to some paths Modify shortest and potentially longest path delays

Reconvergent Path Timing DI

CSS-DI for Edge-Sensitive I M if I m I m I M

CSS-DI for Level-Sensitive I m if I M I m I M

Implementation Highlights Corner cases for delays Stand-alone frameworks –Edge-sensitive –Level-sensitive Reasonable run-times –Under 2 minutes with barrier optimizer

Edge-Sensitive Results Improvement CLOCK SKEW SCHEDULING28% CLOCK SKEW SCHEDULING WITH DELAY INSERTION 34%

Level-Sensitive Results Improvement CLOCK SKEW SCHEDULING29% CLOCK SKEW SCHEDULING WITH DELAY INSERTION 34%

Quantitative Summary Delay insertion applicable to –41% of edge-triggered ISCAS’89 circuits –34% of the level-sensitive Improvement over conventional CSS –10% for edge-triggered (26% when applicable) –9% for level-sensitive (27% when applicable)

Conclusions Delay insertion to logic –Systematic Requires topological analysis –Linear, cycle, reconvergent Practical requirements –Design budget for delay insertion –Discrete delay values –Placement

DELAY INSERTION METHOD IN CLOCK SKEW SCHEDULING QUESTIONS?

Clock Period Minimization Problem - 1 Objective function : min T Problem variables –For each register R i Earliest/latest arrival times a i, A i Earliest/latest departure times d i, D i Clock signal delay t i

Clock Period Minimization Problem - 2 Problem Parameters –For each register R i Clock-to-output delay D CQ Data-to-output D DQ Setup time S i Hold time H i –For each local data path R i  R j Data propagation time D P if

Practical Causes of Clock Skew Size Mismatches –Buffer Size, Interconnect length Process Variations –L eff, T ox etc. Temperature Gradients Power Supply Voltage Drop