Lecture 13 ES 210 Latches and Flip-Flops Jack Ou, Ph.D.

Using a Latch as a Memory Element Caution for a D latch: once a clock enables a D latch, the output changes as soon as the input changes – this is not desirable if you do not want the output to change continuously and all the latches use a common clock.

Uses of Flip-flops

D Flip-Flop

Negative Edge triggered D Flip-Flop Clk=0 0 1 Q=Y hold

Negative Edge triggered D Flip-Flop Clk=1 1 0 Y=D hold

Negative Edge Triggered D Flip- Flop CK of latch 1 CK of latch 2 OUT=X Y=D 2: Hold 1: Track 1:hold 2:track 1 2 1:hold 2:track Q=Y Not enough time for D→Y →Q Q will hold steady The value that is produced at the output of the flip-flop is the value that was stored in master stage immediately before the negative edge Occurred.

Positive Edge D-Flop 1 2 CK of latch 2 CK of latch 1 X X=IN OUT=X 1: Hold 2: Track 2:hold 1:track 2:hold 1:track

Timing Diagram

Definition Setup time: the time that the incoming data must be stable before the clock arrives Hold time: the length of time that the data remains stable after the clock arrives for proper operation If the data is stable before the setup time and continues to be stable after the hold time, the flop will work properly. If the data arrives within the period designated by the setup and hold times, the flop may or may not capture the correct value.

CLK-Q The delay from the time that the clock arrives to the point that the output stabilizes. In reality the data must arrive at the setup time before the clock hits and the output is valid after the CLK-Q delay.

Question How would you change a negative edge triggered flip-flop to a positively edge triggered flip-flop?

D-Type Positive Edge Triggered Flip-Flop (CLK=0) CLK =0, maintain the present state

D-Type Positive Edge Triggered Flip-Flop 0 0→ → 0 Q changes D=0 as Clk=0→ 1

D-Type Positive Edge Triggered Flip-Flop 1 0→ 1 1 → 0 1 → 1 Q changes D=1 as Clk=0→ 1

D-Type Positive Edge Triggered Flip-Flop 0 → 1 1 S The flip-flop is unresponsive to changes in D 1 1 D=0→ 1 as Clk=1 S’ Please explore different possible value of S on your own. This will work even for S=R=1 and S=R=0.

Symbol of D Flip-Flops

reset and preset When power is first turned on, the state of the flip-flops is unknwon. – Reset is used to initialize the output to a 0. – Preset is used to initialize the output to a 1.

Reset Feature

D Flip-flop with reset Typo in the book. Should be 1 instead.

JK Flip-Flops D=JQ’+K’Q The next value of D is determined by JQ’+KQ. At the rising edge of D Flip-flop, Q is updated with the value of D. Positive edge D flip-flop

D=JQ’+K’Q J=1,K=1→D=Q’ J=0, K=0 →D=Q J=0, K=1 →D=0 J=1, K=0 →D=Q’+Q=1

Differences Between a D Flip- Flop and JK Flip-Flop

T Flip-Flop

T Flip-Flop from D Flip-Flop D=TQ’+T’Q If T=1, D=Q’ If T=0, D=Q. Q is updated with D at the next rising edge.

DFF with reset

Phase Frequency Detector

Delay B by 10 ns

Delay A by 10 ns

Clk_A=20 MHz, Clk_B=21 MHz

Clk_A=21 MHz, Clk_B=20 MHz

Clk_A=20 MHz and Clk_B=20 MHz