Latches and Flip-Flops ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning.

Slides:



Advertisements
Similar presentations
Chapter 6 -- Introduction to Sequential Devices. The Sequential Circuit Model Figure 6.1.
Advertisements

Sequential Digital Circuits Dr. Costas Kyriacou and Dr. Konstantinos Tatas.
1 Lecture 14 Memory storage elements  Latches  Flip-flops State Diagrams.
Latches CS370 –Spring 2003 Section 4-2 Mano & Kime.
Flip-Flops Basic concepts. 1/50A. Yaicharoen2 Flip-Flops A flip-flop is a bi-stable device: a circuit having 2 stable conditions (0 or 1) 3 classes of.
CENG 241 Digital Design 1 Lecture 8 Amirali Baniasadi
ECE 331 – Digital System Design Latches and Flip-Flops (Lecture #17) The slides included herein were taken from the materials accompanying Fundamentals.
Sequential Logic Latches and Flip-Flops. Sequential Logic Circuits The output of sequential logic circuits depends on the past history of the state of.
Sequential Circuits1 DIGITAL LOGIC DESIGN by Dr. Fenghui Yao Tennessee State University Department of Computer Science Nashville, TN.
Digital Electronics Chapter 5 Synchronous Sequential Logic.
Flip-Flops and Related Devices Wen-Hung Liao, Ph.D.
CMPUT Computer Organization and Architecture II1 CMPUT329 - Fall 2003 Topic A: Flip-Flops José Nelson Amaral.
1 Chapter 8 Flip-Flops and Related Devices. 2 Figure 8--1 Two versions of SET-RESET (S-R) latches S-R (Set-Reset) Latch.
Nonlinear & Neural Networks LAB. CHAPTER 11 LATCHES AND FLIP-FLOPS 11.1Introduction 11.2Set-Reset Latch 11.3Gated D Latch 11.4Edge-Triggered D Flip-Flop.
Sequential Circuits : Part I Read Sections 5-1, 5-2, 5-3.
Computing Machinery Chapter 5: Sequential Circuits.
1 © 2014 B. Wilkinson Modification date: Dec Sequential Logic Circuits – I Flip-Flops A sequential circuit is a logic components whose outputs.
EKT 124 / 3 DIGITAL ELEKTRONIC 1
Figure 7–1 Two versions of SET-RESET (S-R) latches
Unit 11 Latches and Flip-Flops Ku-Yaw Chang Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh.
Chapter 10 Flip-Flops and Registers Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz.
ECE 331 – Digital System Design Flip-Flops and Registers (Lecture #18) The slides included herein were taken from the materials accompanying Fundamentals.
CS 140 Lecture 7 Professor CK Cheng 4/23/02. Part II. Sequential Network (Ch ) 1.Flip-flops SR, D, T, JK, 2.SpecificationState Table 3.Implementation.
ENGIN112 L20: Sequential Circuits: Flip flops October 20, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 20 Sequential Circuits: Flip.
CS 151 Digital Systems Design Lecture 20 Sequential Circuits: Flip flops.
Sequential Circuits. 2 Sequential vs. Combinational Combinational Logic:  Output depends only on current input −TV channel selector (0-9) Sequential.
A clocked synchronous state-machine changes state only when a triggering edge or “tick” occurs on the clock signal. ReturnNext  “State-machine”: is a.
CS 140 Lecture 8 Professor CK Cheng 10/22/02. Part II. Sequential Network 1.Flip-flops SR, D, T, JK, State Table Characteristic Eq. Q(t+1) = f(x(t), Q(t)).
Flip-Flops Section 4.3 Mano & Kime. D Latch Q !Q CLK D !S !R S R X 0 Q 0 !Q 0 D CLK Q !Q Note that Q follows D when the clock in high, and.
Unit 11 Latches and Flip-Flops Ku-Yaw Chang Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh.
Flip Flops. Clock Signal Sequential logic circuits have memory Output is a function of input and present state Sequential circuits are synchronized by.
Unit 11 Latches and Flip-Flops Ku-Yaw Chang Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh.
Digital Electronics and Computer Interfacing Tim Mewes 3. Digital Electronics.
Components used in the the Project J-K Flip Flop Switch Power Alternator 7-Segment Display Coded Decimal (BCD) Display.
Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic SEQUENTIAL LOGIC.
Astable: Having no stable state. An astable multivibrator oscillates between two quasistable states. Asynchronous Having no fixed time relationship Bistable.
Introduction to Sequential Logic Design Flip-flops.
Sequential Arithmetic ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning.
Introduction to Sequential Logic Design Flip-flops.
D Latch Delay (D) latch:a) logic symbolb) NAND implementationc) NOR implementation.
Unit 11 Latches and Flip-Flops Fundamentals of Logic Design By Roth and Kinney.
Flip Flops 3.1 Latches and Flip-Flops 3 ©Paul Godin Created September 2007 Last Edit Aug 2013.
Sequential Design Basics. Lecture 2 topics  A review of devices that hold state A review of Latches A review of Flip-Flops 8/22/2012 – ECE 3561 Lect.
Karnaugh Maps ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning.
Chapter 10 Flip-Flops and Registers 1. Objectives You should be able to: Explain the internal circuit operation of S-R and gated S-R flip-flops. Explain.
1 COMP541 Sequential Circuits Montek Singh Feb 1, 2007.
1 Synchronous Sequential Logic Sequential Circuits Every digital system is likely to have combinational circuits, most systems encountered in practice.
Digital Electronics and Computer Interfacing Tim Mewes 3. Digital Electronics.
CEC 220 Digital Circuit Design Latches and Flip-Flops Monday, March 03 CEC 220 Digital Circuit Design Slide 1 of 19.
VHDL for Sequential Logic
Chapter 6 – Digital Electronics – Part 1 1.D (Data) Flip Flops 2.RS (Set-Reset) Flip Flops 3.T Flip Flops 4.JK Flip Flops 5.JKMS Flip Flops Information.
Introduction ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Thomson Engineering.
CEC 220 Digital Circuit Design Latches and Flip-Flops
Boolean Algebra ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning.
Flip Flops 3.1 Latches and Flip-Flops 3 ©Paul Godin Created September 2007 Last Edit Aug 2013.
CENG 241 Digital Design 1 Lecture 7 Amirali Baniasadi
Dept. of Electrical Engineering
7. Latches and Flip-Flops Digital Computer Logic.
CHAPTER 11 LATCHES AND FLIP-FLOPS This chapter in the book includes: Objectives Study Guide 11.1Introduction 11.2Set-Reset Latch 11.3Gated D Latch 11.4Edge-Triggered.
©2010 Cengage Learning SLIDES FOR CHAPTER 11 LATCHES AND FLIP-FLOPS Click the mouse to move to the next page. Use the ESC key to exit this chapter. This.
UNIT 11 LATCHES AND FLIP-FLOPS Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter in the book includes: Objectives.
Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey All rights reserved. Digital Fundamentals, Tenth Edition Thomas.
DIGITAL LOGIC CIRCUITS 조수경 DIGITAL LOGIC CIRCUITS.
Digital Logic Vol. 2 Presented by Leo Pleše ScienceUp.org.
Digital Design: With an Introduction to the Verilog HDL, 5e M. Morris Mano Michael D. Ciletti Copyright ©2013 by Pearson Education, Inc. All rights reserved.
Digital Design Lecture 9
FLIP FLOPS.
Elec 2607 Digital Switching Circuits
Lecture No. 24 Sequential Logic.
Sequential Digital Circuits
Presentation transcript:

Latches and Flip-Flops ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning

311_112 Set-Reset Latch S R Q' Q

311_113 Set-Reset Latch S R Q' Q

311_114 Set-Reset Latch S R Q' Q / 1 / 0 / 1 / 0/ 1

311_115 0 / 1 / 0 0 / 1/ 0 Set-Reset Latch S R Q' Q / 0 / 1

Switch Debouncing 6

D Latch 311_117

Edge-Triggered D Flip-Flop 311_118

Timing Parameters 311_119

J-K and T Flip-Flops 311_1110

J-K FF Timing Diagram 311_1111

T FF Timing Diagram 311_1112 (Falling-Edge Triggered)

Additional Inputs 311_1113

Sequential Circuits 311_1114

Summary  Latches S-R (Set-Reset) D (Data)  Flip-Flops (Edge-Triggered) D (Data) J-K (Set-Reset-Toggle) T (Toggle) 311_1115