Latches and Flip-Flops ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning
311_112 Set-Reset Latch S R Q' Q
311_113 Set-Reset Latch S R Q' Q
311_114 Set-Reset Latch S R Q' Q / 1 / 0 / 1 / 0/ 1
311_115 0 / 1 / 0 0 / 1/ 0 Set-Reset Latch S R Q' Q / 0 / 1
Switch Debouncing 6
D Latch 311_117
Edge-Triggered D Flip-Flop 311_118
Timing Parameters 311_119
J-K and T Flip-Flops 311_1110
J-K FF Timing Diagram 311_1111
T FF Timing Diagram 311_1112 (Falling-Edge Triggered)
Additional Inputs 311_1113
Sequential Circuits 311_1114
Summary Latches S-R (Set-Reset) D (Data) Flip-Flops (Edge-Triggered) D (Data) J-K (Set-Reset-Toggle) T (Toggle) 311_1115