NATIONAL POLYTECHNIC INSTITUTE COMPUTING RESEARCH CENTER IPN-CICMICROSE Lab Design and implementation of a Multimedia Extension for a RISC Processor Eduardo Jonathan Martínez Montes Prof. Marco Antonio Ramírez Salinas

I.Background 1.Motivation 2.Multimedia applications 3.State of the art II.Problem Description 1.Overview 2.SISD 3.SIMD 4.SISD vs SIMD 5.Saturation arithmetic 6.Example 7.Instruction format III. Objective 1.Main objective 2.Specific objectives OUTLINE IPN-CICMICROSE Lab2 IV. Hypothesis 1.Multimedia support MDMX Vector to vector arithmetic V. Technical Merits 1.Data path 2.Vector units

IPN-CICMICROSE Lab3 BACKGROUNDMotivation Lagarto is a superscalar embedded processor, now in develop by the HPC research team of CIC-IPN. The goal of this effort is to be used to help in the research and teaching. This processor require the design and build many blocks, so that, this project is part of a bigger project.

IPN-CICMICROSE Lab4 BACKGROUNDMotivation (cont.)

IPN-CICMICROSE Lab5 BACKGROUNDMotivation (cont.)

IPN-CICMICROSE Lab6 BACKGROUNDMultimedia applications Photo edition Video edition Rendering Video games

IPN-CICMICROSE Lab7 State of the art AVX2 - Intel 2013 Sandy Bridge y Bulldozer - Intel y AMD 2011 Advanced Vector Extensions (AVX) - Intel 2008 SSE4 - Intel 2006 SSE y SSE2 - AMD 2004 SSE3 - Intel 2004 Advance 3DNow! (3DNow! 2) - AMD 2003 AltiVec - IBM 2002 SSE2 - Intel DNow!. - AMD 2000 Streaming SIMD Extensions (SSE)- Intel 1999 Pentium II (MMX)- Intel 1998 AltiVec - Motorola BACKGROUND

IPN-CICMICROSE Lab8 PROBLEM DESCRIPTIONOverview Multimedia Extension is a vector machine that is embedded in situ with the main Superscalar Processor, it is used for deal with multimedia applications. Lagarto processor Main processor Multimedia extension

IPN-CICMICROSE Lab9 PROBLEM DESCRIPTIONSISD Single Instruction Single Data is a term referring to a computer architecture In which a single processor executes a single instruction stream.

IPN-CICMICROSE Lab10 PROBLEM DESCRIPTIONSIMD Single Instruction Multiple Data is a class of parallel computer. It describes computers with multiple processing elements that perform the same operation on multiple data points simultaneously. These machines exploit data level parallelism.

IPN-CICMICROSE Lab11 SISD vs SIMDPROBLEM DESCRIPTION

IPN-CICMICROSE Lab12 Saturation arithmeticPROBLEM DESCRIPTION It is a version of arithmetic in which all operations such as addition and multiplication are limited to a fixed range between a minimum and a maximum value. If the result of an operation is greater than the maximum, it is set to the maximum. On the other hand, if it is below the minimum, it is clamped to the minimum value = = =0

IPN-CICMICROSE Lab13 Example Example: get negative image PROBLEM DESCRIPTION

IPN-CICMICROSE Lab14 SISD Processing Example (cont.)PROBLEM DESCRIPTION

IPN-CICMICROSE Lab15 SIMD Processing Example (cont.)PROBLEM DESCRIPTION

IPN-CICMICROSE Lab16 Instruction formatHYPOTESIS Co-processor instruction COP1= COP2=010010

IPN-CICMICROSE Lab17 Instruction format (cont.)HYPOTESIS Data format and item chooser

IPN-CICMICROSE Lab18 HYPOTESIS Source 2 Source 1 Destination Instruction format (cont.)

IPN-CICMICROSE Lab19 HYPOTESISInstruction format (cont.)

IPN-CICMICROSE Lab20 OBJECTIVEObjectives General Objective Design a multimedia extension unit for a RISC processor (Lagarto). Specific Objectives  Design a vector adder w/wo saturation arithmetic.  Design a multiplier w/wo saturation arithmetic.  Implement the complete Instruction set of the MIPS Digital Media extension (MDMX).

IPN-CICMICROSE Lab21 HYPOTESISMIPS Digital Media Extension Lagarto II processor with:  MDMX supports video, audio, and graphics pixel processing. MDMX is not part of the MIPS Instruction Set. A processor that implements the MDMX must implement the MIPS-V ISA  MIPS MDMX is not intended for general purpose computing. Software support is via shared libraries and assembly language only.

IPN-CICMICROSE Lab22  MDMX shares a register file with the Floating Point Unit. Data is moved between the shared register file and memory with existing Floating Point Load and Store double operations.  Registers are interpreted in two formats: Quad Half and Oct Byte format.  MDMX also shared the 8 Floating Point Condition Code bites.  MDMX has a private 192 bit accumulator register. HYPOTESISMIPS Digital Media Extensión (cont.)

IPN-CICMICROSE Lab23 Vector to vector arithmeticHYPOTESIS

IPN-CICMICROSE Lab24 Data pathTECHNICAL MERITS

IPN-CICMICROSE Lab25 TECHNICAL MERITSVector units  Vector adder w/wo saturation arithmetic.  Vector subs tractor w/wo out saturation arithmetic.  Vector multiplier w/wo out saturation arithmetic.  Instruction vector Queue.  Vector Load/Store Queue.

IPN-CICMICROSE Lab26 Q&A