hArtes Overview Holistic Approach to Reconfigurable real Time Embedded Systems

- 2 - What’s hArtes? hArtes: FP6 applied research integrated project (IP) Started on 01 Sept 2006  currently in specification development phase 17.3 M€ cost, M€ funding 61% industry, 39% university 3 years duration140 person month 14 Partners, 5 Nations 6 Universities, 6 Companies, 2 Research Centers hArtes web site: (under construction)

- 3 - hArtes objectives Develop a toolchain and a methodology supporting effective automatic or semi-automatic design of complex heterogeneous embedded systems. Design a scalable heterogeneous and reconfigurable hardware platform that can be re-targeted to produce optimized real-time embedded systems. Validate the tool chain on a set of innovative applications in the audio and video field “To develop the next generation of technologies, methods and tools for modelling, design, and implementation and operation of hardware/software systems embedded in intelligent devices. An end-to-end systems vision should allow building cost-efficient ambient intelligence systems with optimal performance, high confidence, reduced time to market and faster deployment.”

- 4 - hArtes: holistic vision Reduce time spent dealing with implementation details OEMThalesFaitalThomson SOLUTIONs Atmel Leaff Scaleo Chip ALGORITHMs Fraunhofer IGD Uni P. Marche Uni d’Avignon TOOLs TU Delft Poli Milano Imperial College Inria Uni Ferrara Strong Industrial / Academic Collaboration to develop tool chain for heterogeneous reconfigurable multichip platforms

- 5 - Objectives of the tool chain Holistic approach: Fill the gap between algorithms, architectures, integration and test groups Facilitate the management of the entire flow, to allow identifying optimisation opportunities hidden in different parts of the design Reduced time to market. Start from high level application description using graphical entry, domain specific languages or C Support the automatic system implementation System flexibility through: Reconfigurability Easier design space exploration to identify the best system solution: from feasibility to optimality Manage product variants

- 6 - hArtes tool chain top level flow

- 7 - Tool chain details TUD Atmel+TUD TUD Imperial Polimi Generic GPP (C+macros) GPP Molen code DSP C code FPGA Annotated CAnnotations C2C Profiling TaskPartitioning TasksTransformation DataRepresentation DecisionMapping CodeGeneration Annotated C GPP compMolenDSP comp C2VHDL ELF obj Bitstream Linker Loader Executable code (ELF)

- 8 - Performance improvement in hArtes

- 9 - hArtes toolchain innovation Innovations of the hArtes tool chain include: a framework that allows implementing novel algorithms for design space exploration, supports design partitioning automation, task transformation, choice of data representation, and metric evaluation for HW and SW components; a system synthesis tool producing near optimal implementations that best exploits the capability of each type of processing element; dynamic HW reconfigurability can be exploited to support system upgrade or adaptation to operating conditions; diagrammatic and textual formats in algorithm description and exploration.

hArtes applications Standard and Legacy applications AND innovative applications for: In car / home / office speech and audio enhancement Wavefield synthesis for audio applications Audio surveillance and control Video applications Allowing: Testing and validation of the tool chain on complex use cases Demonstration of the achievements

hArtes Applications ACIS = Advanced Car Information System. Includes advanced audio, speech processing enhancement and speech / speaker recognition Immersive audio. Includes audio acquisition and reproduction for different environments Video processing. Includes legacy video and challenging video transcoding

Advanced Car Information System (ACIS)

hArtes ACIS on the road hArtes based ACIS pre other systems connections (radio-TV, GPS, UMTS, network, etc.) media storage microphones loudspeakers Windows PC hARTES platform other sys (cabin) remote web access ampli

Immersive audio

hArtes application platform hypothesis

hArtes HW platform Scope of the HW platform: Provide a flexible, reconfigurable platform for the selected application domain where the hArtes tool chain can be exercised. Must provide an heterogeneous, reconfigurable platform and the appropriate set of interfaces. Detailed specification ongoing in strict relation with the Application partners

HDK dissemination initiative HDK FREE - hArtes Development Kit with Floating point for Real time Embedded Equipment Objective: academic + SME dissemination & hands-on tool for workshops

Consortium composition Partners: INDUSTRY: Atmel (it), FAITAL (it), Thales (fr), Thomson (fr) SME: LEAFF (it), Scaleo Chip (fr) ACADEMIA: TU Delft (nl), PoliMi (it), UNIVPM (it), INRIA (fr), Fraunhofer (de), Imperial College (uk), UNIFE(it), Université d’Avignon-LIA (fr)

Partners role Applications UNIVPM, FAITAL, Thales, Fraunhofer, Thomson, LIA Tools / methodologies: TU Delft, PoliMi, Imperial College, INRIA, LEAFF Hardware: Atmel, UNIFE, Scaleo Chip Integration / Proof of concept Atmel, UNIVPM, FAITAL, Thales, Fraunhofer, Thomson

Partners role

Project Duration/Budget Project Duration: 3 Years Project Budget: 17 M€ 10.5 M€ Funding –Biggest funding in Embedded Systems –Highest evaluation score (27) Work Packages: WP0. Project management. WP1. Requirements for tools and target applications. WP2. Methodology and tool development. WP3. Demonstrations and Evaluations. WP4. System Integration and Validation. WP5. Exploitation and dissemination.