MD, Entwicklung von Powerpointfolien Institut für Angewandte Mikroelektronik und Datentechnik Fachbereich Elektrotechnik und Informationstechnik, Universität Rostock Conditional Sum Adder (COSA)

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Classification of Adders ( Source: Binary Adder Architectures – Reto Zimmermann )

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Gate delay (ns)* Gate count* Gate delay X Gate count(normalised)*

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Power Delay Analysis Post – Layout Power (µW / MHz)Post – Layout PDP (normalised) ( * Source: Binary Adder Architectures – Reto Zimmermann )

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Conditional Sum Adder Sklansky – elements: Conditional Cells & Multiplexers Each bit of adder – 1 Conditional Cell Generation of s0,s1 and c0,c1 Selection – Multiplexers

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Implementation of a Conditional Cell

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Example The conditional sums that would be generated by the first stage of a conditional sum adder in adding to

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Example The remaining stages in adding to

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Conclusions Stages = logn + 1 One of the fastest adder logics PDP minimisation through better design constraints Transmission Gate Logic to be considered

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Thank you Very Much Prof.Dr.Ing. Dirk Timmermann Dipl.-Ing. Frank Sill Dipl.-Ing. Harald Widiger Dipl.-Ing. Stephan Kubisch Dipl.-Ing. Ronald Hecht

MD, Entwicklung von Powerpointfolien Institut für Angewandte Mikroelektronik und Datentechnik Fachbereich Elektrotechnik und Informationstechnik, Universität Rostock Presentation by Vinod Kumar Kothapalli Computational Engineering ( )