1 Efficient Analytical Determination of the SEU- induced Pulse Shape Rajesh Garg Sunil P. Khatri Department of ECE Texas A&M University College Station, TX

2 Radiation Particle Strike What is a radiation particle strike? What is a radiation particle strike? Neutron, proton and heavy cosmic ions Neutron, proton and heavy cosmic ions Ions strike diffusion regions Ions strike diffusion regions Deposit charge Deposit charge Results in a voltage spike Results in a voltage spike Can result in a logical error – Can result in a logical error – Single Event Upset (SEU) or Soft Errors Radiation particle strike is modeled by a current pulse as Radiation particle strike is modeled by a current pulse as where: Q is the amount of charge deposited where: Q is the amount of charge deposited   is the collection time constant   is the ion track establishment constant   is the ion track establishment constant

3 Outline Introduction Introduction Previous Work Previous Work Approach Approach Classification of Radiation Particle Strikes Classification of Radiation Particle Strikes Our Model Our Model Experimental Results Experimental Results Conclusions Conclusions

4 Introduction Modern VLSI Designs Modern VLSI Designs Vulnerable to noise effects- crosstalk, SEU, etc Vulnerable to noise effects- crosstalk, SEU, etc Single Event Upsets (SEUs) or Soft Errors Single Event Upsets (SEUs) or Soft Errors Troublesome for both memories and combinational logic Troublesome for both memories and combinational logic Becoming increasingly problematic even for terrestrial designs Becoming increasingly problematic even for terrestrial designs Applications demand reliable systems Applications demand reliable systems Need to efficiently design radiation tolerant circuits Need to efficiently design radiation tolerant circuits Selectively harden sensitive gates in a circuits Selectively harden sensitive gates in a circuits Gate which significantly contribute to soft error failure rate of circuit Gate which significantly contribute to soft error failure rate of circuit

5 Introduction 3 masking factors determine sensitivity of gates 3 masking factors determine sensitivity of gates Logical, temporal and electrical masking Logical, temporal and electrical masking Logical and temporal can be obtained without electrical simulations Logical and temporal can be obtained without electrical simulations Electrical masking need electrical simulations Electrical masking need electrical simulations Depends upon on the electrical properties of all gates on sensitized path from gate to primary outputs (POs) Depends upon on the electrical properties of all gates on sensitized path from gate to primary outputs (POs) Important to consider these factors for efficient circuit hardening Important to consider these factors for efficient circuit hardening Need efficient analysis and simulation approaches Need efficient analysis and simulation approaches Analyze circuits early in design flow Analyze circuits early in design flow Based on the results of the analysis, we can efficiently achieve required tolerance while minimizing overheads Based on the results of the analysis, we can efficiently achieve required tolerance while minimizing overheads

6 SEU Simulation and Analysis Electrical masking effects can be determined by SPICE based simulation of SEU events Electrical masking effects can be determined by SPICE based simulation of SEU events Most accurate circuit simulation possible Most accurate circuit simulation possible Computationally expensive Computationally expensive Too many scenarios required to be simulated Too many scenarios required to be simulated Amount of charge dumped Amount of charge dumped State of circuit inputs State of circuit inputs Need to simulate all nodes in a circuit Need to simulate all nodes in a circuit Hence we need an efficient and accurate approach to determine the shape of the radiation induced voltage glitch Hence we need an efficient and accurate approach to determine the shape of the radiation induced voltage glitch This is the focus of this talk This is the focus of this talk

7 Previous Work Device-level simulation: Dodd et. al 1994, etc Device-level simulation: Dodd et. al 1994, etc Accurate but very time consuming Accurate but very time consuming Not helpful for circuit hardening Not helpful for circuit hardening Logic-level simulation: Cha et. al 1996 Logic-level simulation: Cha et. al 1996 Abstract transient faults by logic-level models Abstract transient faults by logic-level models Gate-level timing simulators are used Gate-level timing simulators are used Highly inaccurate Highly inaccurate Circuit-level simulation: Circuit-level simulation: Intermediate between device and logic level simulation Intermediate between device and logic level simulation However, this is still very time consuming since a large number of scenarios need to be modeled However, this is still very time consuming since a large number of scenarios need to be modeled

8 Previous Work Shih et. al 1992 solve transistor non-linear differential equation using infinite power series Shih et. al 1992 solve transistor non-linear differential equation using infinite power series Computationally expensive Computationally expensive Dahlgren et. al 1995 presented switch level simulator Dahlgren et. al 1995 presented switch level simulator Electrical simulations are performed to obtain the pulse width of a voltage glitch for given R and C values of a gate Electrical simulations are performed to obtain the pulse width of a voltage glitch for given R and C values of a gate Pulse width for other R and C values are obtained using linear relationship between the obtained pulse width and the new R and C values Pulse width for other R and C values are obtained using linear relationship between the obtained pulse width and the new R and C values Cannot be used for different values of Q Cannot be used for different values of Q Mohanram 2005 reports a closed form model for SEU induced transient simulation for combinational circuits Mohanram 2005 reports a closed form model for SEU induced transient simulation for combinational circuits Linear RC gate model is used Linear RC gate model is used Ignores the contribution of   in i seu (t) – we found that this results in 40% root mean square percentage error in voltage glitch Ignores the contribution of   in i seu (t) – we found that this results in 40% root mean square percentage error in voltage glitch Both these factors result in higher inaccuracy. Both these factors result in higher inaccuracy. Our approach has a 4.5% error Our approach has a 4.5% error

9 Objective Develop an analytical model for waveform of a radiation-induced voltage glitch in combinational circuits Develop an analytical model for waveform of a radiation-induced voltage glitch in combinational circuits Closed form analytical expression for the pulse shape of voltage glitch Closed form analytical expression for the pulse shape of voltage glitch Accurate and efficient Accurate and efficient Applicable to Applicable to Any logic gate Any logic gate Different gate sizes Different gate sizes Different gate loading Different gate loading Incorporates the contribution of the   time constant Incorporates the contribution of the   time constant Can be easily integrated in a design flow Can be easily integrated in a design flow Can be used with a glitch propagation tool to evaluate the effect (at the circuit Primary Outputs) of a radiation strike at any internal gate G Can be used with a glitch propagation tool to evaluate the effect (at the circuit Primary Outputs) of a radiation strike at any internal gate G So we can find (and harden) sensitive gates in a design So we can find (and harden) sensitive gates in a design

10 Our Approach Consider a radiation particle strike at the output of INV1 Consider a radiation particle strike at the output of INV1 Implemented using 65nm PTM with VDD=1V Implemented using 65nm PTM with VDD=1V Radiation strike: Q =150fC,   =150ps &   =50ps Radiation strike: Q =150fC,   =150ps &   =50ps Models Radiation Particle Strike M1 in Linear M2 in Cutoff M1 in Saturation M2 in Cutoff M1 in Saturation M2 in Saturation M1 and M2 operate in different regions during radiation-induced transients We estimate the radiation-induced voltage waveform by modeling these regions INV1 cannot be modeled accurately by a linear RC model (as was done in several previous approaches) M1 in Saturation M2 in Saturation M2’s Drain-Bulk diode is ON

11 Classification of Radiation Strike INV1 can operate in 4 different cases depending upon voltage glitch magnitude V GM (=V a ) INV1 can operate in 4 different cases depending upon voltage glitch magnitude V GM (=V a ) Case 1: V GM ≥ VDD + 0.6V Case 1: V GM ≥ VDD + 0.6V Case 2: VDD+|V TP | ≤ V GM < VDD + 0.6V Case 2: VDD+|V TP | ≤ V GM < VDD + 0.6V Case 3: 0.5*VDD ≤V GM <VDD+|V TP | Case 3: 0.5*VDD ≤V GM <VDD+|V TP | Case 4: V GM < 0.5*VDD Case 4: V GM < 0.5*VDD Different analytical models are applicable to different cases to compute pulse waveform of the voltage glitch

Use Case 2 equations to estimate the shape of voltage glitch Model Overview Given a gate G, its input state, the gates in the fanout of G and Q,   and   Determine the value of V GM using gate current model for Vdsat ≤ Va ≤ VDD – V |TP| If Case==4 No voltage glitch YesNo Use Case 3 equations to estimate the shape of voltage glitch Cell library data I out (V in,V DS ) for V GS =1 and 0, C G and C D If Case==3 Determine the value of V GM using gate current model for Va ≥ VDD – V |TP| Yes If Case==2 YesNo Use Case 1 equations to estimate the shape of voltage glitch No

Integrate Equation 1 from (0, 0) to (V dsat, T1 sat ) with If V GM > 0.5*VDD then there is a glitch Load current model of INV with input at VDD Load current model of INV with input at VDD Differential equation for radiation induced voltage transient at output of INV1 Differential equation for radiation induced voltage transient at output of INV1 (1) (1) Again integrate Equation 1 with initial condition (V dsat, T1 sat ) and with Now V GM = V a (T V GM ) If 0.5*VDD ≤ V GM < VDD + |V TP | then Case 3 is applicable otherwise need to resolve between Case 1 and Case 2 13 Obtain T V GM by differentiating V a (t) and solving dV a (t)/dt = 0 Voltage Glitch Magnitude (V GM ) t Va(t)Va(t) Green  Known Yellow  Unknown T1 sat V dsat Solve for T1 sat T V GM V GM

14 Derivation for Case 3 For Case 3: 0.5*VDD ≤ V GM < VDD + |V TP | For Case 3: 0.5*VDD ≤ V GM < VDD + |V TP | PMOS transistor never turns ON PMOS transistor never turns ON Already know voltage expressions for time intervals (0,T1 sat ) and (T1 sat,T2 sat ) Already know voltage expressions for time intervals (0,T1 sat ) and (T1 sat,T2 sat )(1) t Va(t)Va(t) Green  Known Yellow  Unknown T1 sat V dsat T V GM V GM T2 sat Solve for T2 sat Integrate Equation 1 from with (V dsat, T2 sat ) as initial condition with Now, the voltage expression is available for t = T2 sat to infinity also

15 Resolving Between Cases 1 and 2 V GM > VDD + |V TP | V GM > VDD + |V TP | Need to re-compute V GM to resolve between Cases 1 and 2 Need to re-compute V GM to resolve between Cases 1 and 2 Find T1 P when Find T1 P when V a (t) = VDD + V |TP| t Va(t)Va(t) Green  Known Yellow  Unknown T1 sat V dsat T V GM V GM VDD + |V TP | T1 P Solve for T1 P Integrate Equation 1 from with (VDD+V |TP|, T1 P ) as initial condition with Obtain T V GM by differentiating V a (t) and solving dV a (t)/dt = 0 Now V GM = V a (T V GM ) If VDD + V |TP| ≤ V GM <VDD then Case 2 is applicable otherwise Case 1 is applicable *Details can be found in the paper

Derivation for Case 2 For Case 2: VDD + V |TP| ≤ V GM < VDD For Case 2: VDD + V |TP| ≤ V GM < VDD Diode never turns ON Diode never turns ON Already know voltage expressions for time intervals (0,T1 sat ), (T1 sat,T1 P ) and (T1 P,T2 P ) Already know voltage expressions for time intervals (0,T1 sat ), (T1 sat,T1 P ) and (T1 P,T2 P ) Solve for T2 P Solve for T2 P Also known for (T2 P, T2 sat ) Also known for (T2 P, T2 sat ) Solve for T2 sat Solve for T2 sat Now integrate Equation 1 with initial condition (V dsat, T2 sat ) similar to Case 3 Now integrate Equation 1 with initial condition (V dsat, T2 sat ) similar to Case 3 Va(t)Va(t) T1 sat V dsat T V GM V GM VDD + |V TP | T1 P Green  Known Yellow  Unknown t T2 P Solve for T2 P Integrate Equation 1 from with (VDD+V |TP|, T1 P ) as initial condition with T2 sat Solve for T2 sat

Derivation for Case 1 For Case 1: V GM ≥ VDD + 0.6V For Case 1: V GM ≥ VDD + 0.6V Diode turns ON and clamps the node voltage to VDD + 0.6V Diode turns ON and clamps the node voltage to VDD + 0.6V Derivation is similar to Case 2 Derivation is similar to Case 2 For (T1 P, T2 P ) the voltage expression is modified to min(VDD + 0.6, V a (t)) For (T1 P, T2 P ) the voltage expression is modified to min(VDD + 0.6, V a (t)) Voltage expression for other time intervals are same as that of Case 2 Voltage expression for other time intervals are same as that of Case 2

18 Experimental Results Implemented our model in Perl Implemented our model in Perl Applied our model to INV, NAND2 and NOR3 Applied our model to INV, NAND2 and NOR3 Using 65nm PTM model card with VDD=1V Using 65nm PTM model card with VDD=1V Characterized each gate for I DS, C G and C D Characterized each gate for I DS, C G and C D For each of these gates, we applied our model For each of these gates, we applied our model For different values of Q,   and   For different values of Q,   and   Different gate sizes and loads Different gate sizes and loads Our model is ~275X faster compared to SPICE Our model is ~275X faster compared to SPICE Results could be improved if implemented in a compiled language Results could be improved if implemented in a compiled language

19 Experimental Results

20 Experimental Results Root mean square percentage (RMSP) error for 3X gates for Q=150fC,   =150ps and   = 50ps Root mean square percentage (RMSP) error for 3X gates for Q=150fC,   =150ps and   = 50ps

21 Experimental Results RMSP error averaged over all possible input states for different gate sizes for Q=150fC,   =150ps and   = 50ps RMSP error averaged over all possible input states for different gate sizes for Q=150fC,   =150ps and   = 50ps Average RMSP error of our model is 4.5% Average RMSP error of our model is 4.5% Much lower than 40% error of the model by Mohanram 2005 Much lower than 40% error of the model by Mohanram 2005

22 Conclusion We presented an analytical model to estimate the shape of the radiation-induced voltage glitch We presented an analytical model to estimate the shape of the radiation-induced voltage glitch Can be used with glitch propagation tools to estimate the voltage glitch at POs Can be used with glitch propagation tools to estimate the voltage glitch at POs Based on this, sensitive gates can be identified and hardened to improve the radiation tolerance of the design Based on this, sensitive gates can be identified and hardened to improve the radiation tolerance of the design This can be done early in the design cycle This can be done early in the design cycle Our model is accurate and efficient Our model is accurate and efficient RMSP error is 5% compared to SPICE RMSP error is 5% compared to SPICE Our method is 275X faster than SPICE Our method is 275X faster than SPICE Our model gains accuracy Our model gains accuracy By using the load current model (and avoiding a linear RC model for the gate) By using the load current model (and avoiding a linear RC model for the gate) By including the contribution of   By including the contribution of  

23 Thank You