EECE **** Embedded System Design

Slides:



Advertisements
Similar presentations
Fakultät für informatik informatik 12 technische universität dortmund Optimizations - Compilation for Embedded Processors - Peter Marwedel TU Dortmund.
Advertisements

- 1 -  P. Marwedel, Univ. Dortmund, Informatik 12, 2003 Universität Dortmund Hardware/Software Codesign.
Hardware/ Software Partitioning 2011 年 12 月 09 日 Peter Marwedel TU Dortmund, Informatik 12 Germany Graphics: © Alexandra Nolte, Gesine Marwedel, 2003 These.
ECE-777 System Level Design and Automation Hardware/Software Co-design
ECOE 560 Design Methodologies and Tools for Software/Hardware Systems Spring 2004 Serdar Taşıran.
Undoing the Task: Moving Timing Analysis back to Functional Models Marco Di Natale, Haibo Zeng Scuola Superiore S. Anna – Pisa, Italy McGill University.
Implementation Approaches with FPGAs Compile-time reconfiguration (CTR) CTR is a static implementation strategy where each application consists of one.
Constraint Systems used in Worst-Case Execution Time Analysis Andreas Ermedahl Dept. of Information Technology Uppsala University.
Programming Languages Marjan Sirjani 2 2. Language Design Issues Design to Run efficiently : early languages Easy to write correctly : new languages.
RUN: Optimal Multiprocessor Real-Time Scheduling via Reduction to Uniprocessor Paul Regnier † George Lima † Ernesto Massa † Greg Levin ‡ Scott Brandt ‡
- 1 -  P. Marwedel, Univ. Dortmund, Informatik 12, 05/06 Universität Dortmund Hardware/Software Codesign.
Overview of PTIDES Project
11 1 Hierarchical Coarse-grained Stream Compilation for Software Defined Radio Yuan Lin, Manjunath Kudlur, Scott Mahlke, Trevor Mudge Advanced Computer.
ECE669 L20: Evaluation and Message Passing April 13, 2004 ECE 669 Parallel Computer Architecture Lecture 20 Evaluation and Message Passing.
Vertically Integrated Analysis and Transformation for Embedded Software John Regehr University of Utah.
RTL Processor Synthesis for Architecture Exploration and Implementation Schliebusch, O. Chattopadhyay, A. Leupers, R. Ascheid, G. Meyr, H. Steinert, M.
System Level Design: Orthogonalization of Concerns and Platform- Based Design K. Keutzer, S. Malik, R. Newton, J. Rabaey, and A. Sangiovanni-Vincentelli.
1 HW/SW Partitioning Embedded Systems Design. 2 Hardware/Software Codesign “Exploration of the system design space formed by combinations of hardware.
CS244-Introduction to Embedded Systems and Ubiquitous Computing Instructor: Eli Bozorgzadeh Computer Science Department UC Irvine Winter 2010.
Define Embedded Systems Small (?) Application Specific Computer Systems.
Chess Review May 10, 2004 Berkeley, CA Platform-based Design for Mixed Analog-Digital Designs Fernando De Bernardinis, Yanmei Li, Alberto Sangiovanni-Vincentelli.
February 21, 2008 Center for Hybrid and Embedded Software Systems Mapping A Timed Functional Specification to a Precision.
November 18, 2004 Embedded System Design Flow Arkadeb Ghosal Alessandro Pinto Daniele Gasperini Alberto Sangiovanni-Vincentelli
A Tool for Partitioning and Pipelined Scheduling of Hardware-Software Systems Karam S Chatha and Ranga Vemuri Department of ECECS University of Cincinnati.
1 Platform-Based Design A paper by Alberto Sangiovanni-Vincentelli EE 249, 11/5/2002 Presenter: Mel Tsai.
UCB November 8, 2001 Krishna V Palem Proceler Inc. Customization Using Variable Instruction Sets Krishna V Palem CTO Proceler Inc.
Trend towards Embedded Multiprocessors Popular Examples –Network processors (Intel, Motorola, etc.) –Graphics (NVIDIA) –Gaming (IBM, Sony, and Toshiba)
Platform-based Design for Mixed Analog-Digital Designs Fernando De Bernardinis, Yanmei Li, Alberto Sangiovanni-Vincentelli May 10, 2004 Analog Platform.
Mahapatra-Texas A&M-Fall'001 Codesign Framework Parts of this lecture are borrowed from lectures of Johan Lilius of TUCS and ASV/LL of UC Berkeley available.
Router modeling using Ptolemy Xuanming Dong and Amit Mahajan May 15, 2002 EE290N.
Kathy Grimes. Signals Electrical Mechanical Acoustic Most real-world signals are Analog – they vary continuously over time Many Limitations with Analog.
- 1 -  P. Marwedel, Univ. Dortmund, Informatik 12, 2003 Universität Dortmund Actual design flows and tools.
Universität Dortmund  P. Marwedel, Univ. Dortmund, Informatik 12, 2003 Hardware/software partitioning  Functionality to be implemented in software.
- 1 - EE898-HW/SW co-design Hardware/Software Codesign “Finding right combination of HW/SW resulting in the most efficient product meeting the specification”
Course Outline DayContents Day 1 Introduction Motivation, definitions, properties of embedded systems, outline of the current course How to specify embedded.
1 VERILOG Fundamentals Workshop סמסטר א ' תשע " ה מרצה : משה דורון הפקולטה להנדסה Workshop Objectives: Gain basic understanding of the essential concepts.
Trigger design engineering tools. Data flow analysis Data flow analysis through the entire Trigger Processor allow us to refine the optimal architecture.
ICOM 5995: Performance Instrumentation and Visualization for High Performance Computer Systems Lecture 7 October 16, 2002 Nayda G. Santiago.
Parallel Programming Models Jihad El-Sana These slides are based on the book: Introduction to Parallel Computing, Blaise Barney, Lawrence Livermore National.
CAD Techniques for IP-Based and System-On-Chip Designs Allen C.-H. Wu Department of Computer Science Tsing Hua University Hsinchu, Taiwan, R.O.C {
Section 10: Advanced Topics 1 M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi.
High Performance Embedded Computing © 2007 Elsevier Lecture 3: Design Methodologies Embedded Computing Systems Mikko Lipasti, adapted from M. Schulte Based.
8-1 Embedded Systems Fixed-Point Math and Other Optimizations.
High Performance Embedded Computing © 2007 Elsevier Chapter 1, part 2: Embedded Computing High Performance Embedded Computing Wayne Wolf.
1 Exploring Custom Instruction Synthesis for Application-Specific Instruction Set Processors with Multiple Design Objectives Lin, Hai Fei, Yunsi ACM/IEEE.
Page 1 Reconfigurable Communications Processor Principal Investigator: Chris Papachristou Task Number: NAG Electrical Engineering & Computer Science.
ESL and High-level Design: Who Cares? Anmol Mathur CTO and co-founder, Calypto Design Systems.
© 2012 xtUML.org Bill Chown – Mentor Graphics Model Driven Engineering.
 Embedded Digital Signal Processing (DSP) systems  Specification with floating-point data types  Implementation in fixed-point architectures  Precision.
L11: Lower Power High Level Synthesis(2) 성균관대학교 조 준 동 교수
- 1 - EE898_HW/SW Partitioning Hardware/software partitioning  Functionality to be implemented in software or in hardware? No need to consider special.
CS244-Introduction to Embedded Systems and Ubiquitous Computing Instructor: Eli Bozorgzadeh Computer Science Department UC Irvine Winter 2010.
Resource Mapping and Scheduling for Heterogeneous Network Processor Systems Liang Yang, Tushar Gohad, Pavel Ghosh, Devesh Sinha, Arunabha Sen and Andrea.
An Introduction to Software Engineering
Blue Brain Project Carlos Osuna, Carlos Aguado, Fabien Delalondre.
Task Graph Scheduling for RTR Paper Review By Gregor Scott.
6. A PPLICATION MAPPING 6.3 HW/SW partitioning 6.4 Mapping to heterogeneous multi-processors 1 6. Application mapping (part 2)
Lecture 12: Reconfigurable Systems II October 20, 2004 ECE 697F Reconfigurable Computing Lecture 12 Reconfigurable Systems II: Exploring Programmable Systems.
COMPUTER ORGANIZATION AND ASSEMBLY LANGUAGE Lecture 19 & 20 Instruction Formats PDP-8,PDP-10,PDP-11 & VAX Course Instructor: Engr. Aisha Danish.
System-level power analysis and estimation September 20, 2006 Chong-Min Kyung.
Architecture Selection of a Flexible DSP Core Using Re- configurable System Software July 18, 1998 Jong-Yeol Lee Department of Electrical Engineering,
Using Cache Models and Empirical Search in Automatic Tuning of Applications Apan Qasem Ken Kennedy John Mellor-Crummey Rice University Houston, TX Apan.
IT-SOC 2002 © 스마트 모빌 컴퓨 팅 Lab 1 RECONFIGURABLE PLATFORM DESIGN FOR WIRELESS PROTOCOL PROCESSORS.
- 1 -  P. Marwedel, Univ. Dortmund, Informatik 12, 05/06 Universität Dortmund Hardware/Software Codesign.
SASI Enforcement of Security Policies : A Retrospective* PSLab 오민경.
Chapter – 8 Software Tools.
Hardware/Software Co-Design of Complex Embedded System NIKOLAOS S. VOROS, LUIS SANCHES, ALEJANDRO ALONSO, ALEXIOS N. BIRBAS, MICHAEL BIRBAS, AHMED JERRAYA.
Multi-cellular paradigm The molecular level can support self- replication (and self- repair). But we also need cells that can be designed to fit the specific.
ASIC Design Methodology
Subject Name: Embedded system Design Subject Code: 10EC74
Presentation transcript:

EECE **** Embedded System Design Chapter 5A: Hardware/Software Codesign

Hardware/Software Codesign

Design productivity gap

Marketing Vice President Emulation & Verification Engineering (EVE) lauro@eve-usa.com © Lauro Rizzatti

Platform-based design Top-Down: Map an instance of the upper platform onto an lower platform considering appropriate constrains. Bottom-Up: Find the appropriate platform levels. Define platform level parameters Platform instances Platform abstraction levels

Platform-based design Few design areas suitable for PBD: System Platform Stack The main application area. The primary notion of PBD originates here. Network Platforms Equivalent to protocol stacks. Analog Platform Performance models, behavioral models and interconnection models. Decouples the application development process from the architectural implementation process.

Iterative approach (1) Guided by performance evaluation

Essentially the same with our flow … System architecture Implementation Refine System behavior Mapping Performance simulation

Overview of design activities Task level concurrency management Which tasks in the final system? High level transformations Transformation that are outside the scope of traditional compilers Hardware/software partitioning Which operation mapped to hardware, which to software? Compilation Hardware-aware compilation Scheduling Performed several times, with varying precision Design space exploration Set of possible designs, not just one.

Merging of tasks Reduced overhead of context switches, More global optimization of machine code, Reduced overhead for inter-process/task communication.

Splitting of tasks No blocking of resources while waiting for input, more flexibility for scheduling, possibly improved result.

Example of a mixed TCM Deadline Deadline Deadline Static (compile-time) methods can ensure WCET feasible schedules, but waste energy in the average case. t E Deadline Task1 …or they can define a probability for violating the deadline. t Deadline Task2 Task3 Mixed methods use compile-time analysis to define a set of possible execution parameters for each task. Runtime scheduler selects the most energy saving, deadline preserving combination. t Deadline

Example of an mixed TCM „Gray-box“: Extract only the information needed for scheduling. Transformations: Merge and/or split task. (Functionality comparable to Cortadella’s approach.) Find Pareto-curves for each task. Runtime scheduler: uses an heuristic to combine the Pareto-curves.

Fundamental considerations of tradeoffs by Brodersen (Berkeley) Bild zeigt das Ergebnis der Simulation eines 12-punkte LMS adapt. Filters. MSE = Mean-Square-Error (Unterschied in der produzierten Ausgabe eins Floating-Point und eines Fix-Point Systems.

Fridge Fixed-Point Programming and Design Environment RWTH Aachen, commercialized by Synopsys as part of the CoCentric tool suite. Uses type definition features of C++ to define abstract data types (i.e. ‘fixed’) Incorporated into SystemC. (It’s used for bit-true simulation.) Needs architecture dependent back-end optimizations.

Fridge Fixed-Point Programming and Design Environment Workflow overview: Input: floating-point algorithm + designer supplied annotations. Conversion. Iterative, feedback through simulation. Back-end exploits architectural features. (i.e. mulh, sat, round) Output: Target optimized integer C code.

Fridge Fixed-Point Programming and Design Environment Conversion steps: Designer annotates some operands (with WL, IWL, …) Hybrid code: Partially converted to fixed-point. Interpolation: Automatic annotate of remaining operands, transfer each operand into fixed-point type. Code Gen.: Generates pure C code. Back End: Optimize for target. Bit-true simulation. DSP Back End

Today’s summary Design-Productivity-Gap: No final remedy available, but step-by-step improvements keep costs in a reasonable range. Platform based design: Reuse is the key. PBD is the systematic approach to it. Task-Concurrency-Management: Optimize the task set. Goals: Non-blocking job execution / Increased energy efficiency. Float-point to Fixed-point: Fixed-point arithmetic uses integer operations  Simpler and faster hardware than for float-point operations.