Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 7, 2012 Transmission Line Scenarios Repeaters in Wiring

Previously Transmission line (LC wire) reflection Unbuffered RC wire delay scales as L 2 –0.5 R wire C wire –0.5 L 2 R u C u Penn ESE370 Fall DeHon 2

Today Transmission Line Scenarios RC (on-chip) Interconnect Buffering Penn ESE370 Fall DeHon 3

Transmission Line Data travels as waves Line has Impedance May reflect at end of line Penn ESE370 Fall DeHon 4

Impedance Change What happens if there is an impedance change in the wire? Z 0 =75 , Z 1 =50  –What reflections and transmission do we get? Penn ESE370 Fall DeHon 5

Z 0 =75, Z 1 =50 At junction: –Reflects V r =(50-75)/(50+75)V i –Transmits V t =(100/(50+75))V i Penn ESE370 Fall DeHon 6

Impedance Change Z 0 =75, Z 1 =50 Penn ESE370 Fall DeHon 7

What happens at branch? Penn ESE370 Fall DeHon 8

Branch Transmission line sees two Z 0 in parallel –Looks like Z 0 /2 Penn ESE370 Fall DeHon 9

Z 0 =50, Z 1 =25 At junction: –Reflects V r =(25-50)/(25+50)V i –Transmits V t =(50/(25+50))V i Penn ESE370 Fall DeHon 10

End of Branch What happens at end? If ends in matched, parallel termination –No further reflections Penn ESE370 Fall DeHon 11

Branch Simulation Penn ESE370 Fall DeHon 12

Branch with Open Circuit? What happens if branch open circuit? Penn ESE370 Fall DeHon 13

Branch with Open Circuit Reflects at end of open-circuit stub Reflection returns to branch –…and encounters branch again –Send transmission pulse to both Source and other branch Sink sees original pulse as multiple smaller pulses spread out over time Penn ESE370 Fall DeHon 14

Open Branch Simulation Penn ESE370 Fall DeHon 15

Open Branch Simulation Penn ESE370 Fall DeHon 16

Bus Common to have many modules on a bus –E.g. PCI slots –DIMM slots for memory High speed  bus lines are trans. lines Penn ESE370 Fall DeHon 17

Multi-drop Bus Ideal –Open circuit, no load Penn ESE370 Fall DeHon 18

Multi-Drop Bus Impact of capacitive load (stub) at drop? –If tight/regular enough, change Z of line Penn ESE370 Fall DeHon 19

Multi-Drop Bus Long wire stub? –Looks like branch may produce reflections Penn ESE370 Fall DeHon 20

Transmission Line Noise Frequency limits Imperfect termination Mismatched segments/junctions/vias/connectors Loss due to resistance in line –Limits length Penn ESE370 Fall DeHon 21

Idea Transmission lines –high-speed –high throughput –long-distance signaling Termination Signal quality Penn ESE370 Fall DeHon 22

Back to RC Wire (on-chip, no L) Penn ESE370 Fall DeHon 23

Delay of Wire Long Wire: 1mm R wire = 60K  for the 1mm) C wire = 0.16 pF  for the 1mm) Driven by inverter –R 0 = 25K  –C 0 = 0.01 fF –Assume velocity saturated, sized W p =W n =1 Loaded by identical inverter Penn ESE370 Fall DeHon 24

Formulate Delay Penn ESE370 Fall DeHon 25 Delay of inverter driving wire? Should be able to do these calculations on final.

Calculate Delay C load = 2 C 0 R buf = R 0 C self =  2 C 0 = 2 C 0 Penn ESE370 Fall DeHon 26

Buffer Middle Delay if add buffer to middle of wire? Penn ESE370 Fall DeHon 27 Should be able to do these calculations on final.

Formulate and Calculate Delay Penn ESE370 Fall DeHon 28

N Buffers Delay for N buffers? Penn ESE370 Fall DeHon 29

Minimize Delay How minimize delay? Differentiate & Solve for N: Penn ESE370 Fall DeHon 30 Equalizes delay in buffer and wire

Calculate: Delay at Optimum Stages for Example R wire = 60K  for the 1mm) C wire = 0.16 pF  for the 1mm) R buf =R 0 = 25K  C self =C load =2(C 0 = 0.01 fF)=0.02fF Penn ESE370 Fall DeHon 31

Segment Length R wire = L×R unit C wire = L×C unit Penn ESE370 Fall DeHon 32

Optimal Segment Length Delay scales linearly with distance once optimally buffered Penn ESE370 Fall DeHon 33

Buffer Size? How big should buffer be? –R buf = R 0 /W –C load = 2 W C 0 (assuming velocity saturation) –C self =  2 W C 0 Penn ESE370 Fall DeHon 34

Implication W R wire = L×R unit C wire = L×C unit  W independent of Length –Depends on technology Penn ESE370 Fall DeHon 35

Delay at Optimum W With  =1, 1+  =2 Same size as first term Penn ESE370 Fall DeHon 36

Ideas Wire delay linear once buffered Optimal buffering matches –Buffer delay –Delay on wire between buffers Penn ESE370 Fall DeHon 37

Admin Final – Friday 12/14, noon, Moore 212 Review – Wednesday, 12/12 –Evening – time announced on piazza Andre out of town until Friday Penn ESE370 Fall DeHon 38