LOGIKAI TERVEZÉS HARDVERLEÍRÓ NYELVEN

Slides:

Advertisements

Similar presentations

What is a Bus? One of the set of conductors (wires, PCB tracks, or connections in an integrated circuit) connecting the various functional units in a computer.

Advertisements

Computer Systems Nat 4/5 Computing Science Computer Structure:

Verilog in transistor level using Microwind

CDA 3100 Recitation Week 11.

Figure 4.1. The function f (x1, x2, x3) =  m(0, 2, 4, 5, 6).

COE 405 Design and Synthesis of DataPath Controllers Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals.

Anurag Dwivedi.  Verilog- Hardware Description Language  Modules  Combinational circuits  assign statement  Control statements  Sequential circuits.

Sumitha Ajith Saicharan Bandarupalli Mahesh Borgaonkar.

1 Workshop Topics - Outline Workshop 1 - Introduction Workshop 2 - module instantiation Workshop 3 - Lexical conventions Workshop 4 - Value Logic System.

DATAPATHS 3) Shifters. 4) Comparators 5) Counters.

Pulse-Width Modulated DAC

1 COMP541 Combinational Logic and Design Montek Singh Jan 30, 2007.

Chapter 0 Introduction to Computing

Arbitrary Waveform Discussion 12.2 Example 34. Recall Divide-by-8 Counter Use q2, q1, q0 as inputs to a combinational circuit to produce an arbitrary.

Counters Discussion 12.1 Example 33. Counters 3-Bit, Divide-by-8 Counter 3-Bit Behavioral Counter in Verilog Modulo-5 Counter An N-Bit Counter.

2-to-1 Multiplexer: if Statement Discussion D7.1 Example 4.

Reconfigurable Computing (EN2911X, Fall07) Lecture 05: Verilog (1/3) Prof. Sherief Reda Division of Engineering, Brown University

Chapter 2. Definition Characteristics ExamplesNon-examples Input Graphic.

Generic Multiplexers: Parameters Discussion D7.5 Example 8.

Quad 2-to-1 Multiplexer Discussion D7.4 Example 7.

MANINDER KAUR RAM and ROM Chips 24-Nov

Read Only Memory (ROM) Number of words Size of word A block diagram of a ROM consisting of k inputs and n outputs is shown below. The inputs provide the.

Module : TASKS, Functions and UDPs in Verilog. Functions Functions are declared with the keywords function and endfunction. Functions are used if all.

Slide 1 5. VHDL/Verilog Operators, Arrays and Indexes.

Chap. 3 Basic Concepts. 2 Basic Concepts Lexical Conventions Data Types System Tasks and Compiler Directives Summary.

Revised: Aug 1, ECE 263 Embedded System Design Lesson 1 68HC12 Overview.

Spring 2007W. Rhett Davis with slight modification by Dean Brock UNCA ECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 11: Memories,

Communications. How do computers work?  Computer is made up of many different parts  Receives input from user  Processes information  Produces an.

Figure 6.1. A 2-to-1 multiplexer.

ECE 2372 Modern Digital System Design

Binary-to-BCD Converter

1 COMP541 Hierarchical Design & Verilog Montek Singh Jan 28, 2010.

Xiang Zhou xz2266 Hao Zheng hz2256 Ran Zheng rz2228 Younggyun Cho yc2704 Touch Pong.

1 Workshop Topics - Outline Workshop 1 - Introduction Workshop 2 - module instantiation Workshop 3 - Lexical conventions Workshop 4 - Value Logic System.

Introduction to Computing Systems from bits & gates to C & beyond Chapter 4 The Von Neumann Model Basic components Instruction processing.

Figure 5.1. Conversion from decimal to binary.. Table 5.1. Numbers in different systems.

Figure 5.1. Conversion from decimal to binary.. Table 5.1. Numbers in different systems.

Microcontroller Presented by Hasnain Heickal (07), Sabbir Ahmed(08) and Zakia Afroze Abedin(19)

Stanford µSequencer December Motivation Control, initialization, and constant maintenance of Avalon peripherals –Perfectly deterministic Microprocessor.

Department of Communication Engineering, NCTU 1 Unit 5 Programmable Logic and Storage Devices – RAMs and FPGAs.

Topics to be covered : How to model memory in Verilog RAM modeling Register Bank.

1 Workshop Topics - Outline Workshop 1 - Introduction Workshop 2 - module instantiation Workshop 3 - Lexical conventions Workshop 4 - Value Logic System.

Module 2.1 Gate-Level/Structural Modeling UNIT 2: Modeling in Verilog.

Module 1.3 Verilog Basics UNIT 1 : Introduction to Verilog Data Types.

EEE2243 Digital System Design Chapter 3: Verilog HDL (Combinational) by Muhazam Mustapha, January 2011.

Computer System Internal components - The processor - Main memory - I / O controllers - Buses External components (peripherals). These include: - keyboard.

1 ALU ports can get input from any of the two registers ALU can perform one of the eight operations Shift unit can perform one of the four possible types.

A Simplified MIPS Processor in Verilog

Digital Logic Design Lecture # 15 University of Tehran.

Digital Circuits Introduction Memory information storage a collection of cells store binary information RAM – Random-Access Memory read operation.

DDRIII BASED GENERAL PURPOSE FIFO ON VIRTEX-6 FPGA ML605 BOARD PART B PRESENTATION STUDENTS: OLEG KORENEV EUGENE REZNIK SUPERVISOR: ROLF HILGENDORF 1 Semester:

Slide 1 3.VHDL/Verilog Description Elements. Slide 2 To create a digital component, we start with…? The component’s interface signals Defined in MODULE.

Chapter 3: Dataflow Modeling Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 3-1 Chapter 3: Dataflow Modeling.

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU 99-1 Under-Graduate Project Design of Datapath Controllers Speaker: Shao-Wei Feng Adviser:

1 To write any register, we need register address and a write signal A 3-bit write address is decoded if write signal is present One of the eight registers.

Digital Logic & Design Dr.Waseem Ikram Lecture No. 43.

COMP211 Computer Logic Design

Verilog Introduction Fall

EMT 351/4 DIGITAL IC DESIGN Week # Synthesis of Sequential Logic 10.

Pulse-Width Modulation (PWM)

SYNTHESIS OF SEQUENTIAL LOGIC

Lecture 9. MIPS Processor Design – Decoding and Execution

Enhancing Data Path M 4-bit Reg X A L U

Division and Modulo 15 Q A = Dividend B = Divisor Q = Quotient = A/B

RTL Design Methodology Transition from Pseudocode & Interface

Basic components Instruction processing

Reconfigurable Computing (EN2911X, Fall07)

Presentation transcript:

LOGIKAI TERVEZÉS HARDVERLEÍRÓ NYELVEN Dr. Oniga István

Memory In this chapter we will show how to implement memory on the Nexys-2 board by using the following six examples: Example 27 - A Verilog ROM Example 28 - Distributed RAM/ROM Example 29 - A Stack Example 30 - Block RAM Example 31 - External RAM Example 32 - External Flash Memory Example 27 will show how to implement a small read-only memory (ROM) using Verilog. For larger memories you can use the Core Generator to implement either distributed RAM (or ROM) that uses the FPGA LUTs (Example 28) or Block RAM that uses the block RAM within the FPGA (Example 30). For even larger memories you can access the 16 Mbytes of external RAM (Example 31) or 16 Mbytes of external flash memory (Example 32), which are on the Nexys-2 board. Example 29 shows how to use distributed RAM to implement a stack.

A Verilog ROM N is the number of bits per ROM word = 8 3-bit address bus, addr[2:0], 8-bit data bus M[7:0] For example contents of the ROM at the address addr[2:0] = 3'b1 10 is 'h6C To implement this ROM in Verilog it is convenient to store the eight bytes as a single 64-bit hex constant as shown below reg [N-l: O] rom [O:N_WORDS-l]; N is the number of bits per ROM word = 8 The parameter N _ WORDS is the number of N-bit words in the ROM = 8 parameter data = ' h00C8F9AF64956CD4;

A Verilog ROM module rom8 ( input wire [2:0] addr , output wire [7:0] M ) ; parameter N = 8; // no. of bits in rom word parameter N_WORDS = 8 ; //no. of words in rom reg [N-1:0] rom [0:N_WORDS-l]; parameter data = 'h00C8F9AF64956CD4; parameter IXLEFT = N*N_WORDS - 1; // left index of data integer i; initial begin for(i=0; i<N_WORDS; i=i+l) rom[i] = data[(IXLEFT-N*i)-:N]; end assign M = rom[addr]; endmodule Part-selector operator: “ - : “ separates the starting bit IXLEFT-N*I from the width (N) counting down “ + : “ would define a width counting up For i=1 => rom[1] = data[(63-8)-:8 = data[55-:8] = data[55:48] wich selects the byte C8

A Verilog ROM simulation

Distributed RAM/ROM Core Generator:

Distributed RAM/ROM Core Generator:

Distributed RAM/ROM The content of the ROM can be defined using a .coe file with the format: ; Example 28 Initialization file for a 16x8 distributed ROM memory_initialization_radix = 16; memory_initialization_vector = 0 C8 F9 AF 64 95 6C D4 39 E7 5A 96 84 37 28 4C;

Distributed RAM/ROM The component dist_rom16 will be created and all files will be generated.

Distributed RAM/ROM simulation