ESA EJSM/JGO Radio & Plasma Wave Instrument (RPWI) Prag meeting Lennart Åhlén

Electric fields Plasma measurements Conductivities BB Plasma waves Radio

Backplane with power distribution, analog and digital interfaces Board size: 20x15cm TBC Connectors: Micro-D type Box : 21x16x12 cm average 4.7mm wall thickness for Al. Distance between Boards: 20mm Main box mechanics

Power Voltages: +3.3VDigital interface supply +1.8V Digital DPU and FPGA core supply +-8VAnalog Software current limiters (msec turn off at latch up) Common ground for all voltages Only one ground in the backplane Total power: 6.6W average 10W peak (100ms) Instrument interfaces Digital: Differential Analog: Single ended (TBC) Satellite interfaces 2 Mbit SpaceWire Single ended (TBC)

Radiation protection Spot shielding should be used for all S/C external electronics Box and spot shielding should be used for the RPWI Box Use of Rad Hard components Box shielding 4.7mm 1.1 kg extra mass needed for 8mm box protection 3kg allocated by ESA for radiation shielding of RPWI Action: Calculations of internal box radiation levels using GEANT 4

Generic Instrument

LP-PWI Bias control, LF wave analyzer and MIME

HFwave analyzer

WHY Should we use the ESA ASICs ? They are guarantied Rad hard ESA will do the paper work ESA will pay for the qualification We will save mass (up to 650g) We may save power that can be used for signal processing We may save money We can convert saved mass into antenna length If they are not delivered in time we blame ESA for the delay

RA-PWI, RWI and LP-PWI Preamplifiers Lennart Åhlen

LP_PWI Preamplifier Specifications: Switchable E-field / Density 100mW power consumption 500kRad Radiation hardend Positive feed back current generator E-field: DC-300Hz +-100V input range DC to 3MHz small signal bandwidth Better than 10^12 input resistance 1nA – 100nA Current Bias range 16 nV/sqr(Hz) noise Density: DC to 10kHz bandwidth 10pA to 100uA input current range +-100V Voltage Bias range New development: Find new low noise Rad hard operational amplifiers Develop a MEMS chip including nano-switches and amplifiers MEMS amplifier 10x10x1mm total mass 4x30g (4x250g)

RA_PWI and RWI Preamplifier FET follower or FET input negative feed back amplifier ? High distortion Limited output range Low power Simple Low distortion Medium power Complex Specifications: 1kHz to 50MHz Bandwidth2 nV/sqr(Hz) noise +-1V input range100mW power consumption Amplifier from Tohoku University 100Hz to 50MHz 0.6W

RPWI Grounding block diagram EMC Actions. Define acceptable satellite RE and CE levels for the frequency range DC to 45 MHz. MIL-STD-462D ECSS-E-ST-20-07C(31July2008)

1.All spacecraft surfaces exposed to the plasma environment shall be sufficiently conductive and grounded. < 5 kohm/sq 2.Small surfaces differential charging potential shall not exceed +-10 V, assuming a plasma current of 5 nA/cm 2 3.The S/C structure shall not be used as return path for power and signals except for sensor signals to avoid common impedance coupling and magnetic disturbances. 4.Isolated receivers and balanced differential signals should be used as subsystem signal interfaces. 5.All active wires shall be twisted with its return wire and loops on circuit boards should be minimize to reduce magnetic disturbances. 6.The spacecraft system shall use a Distributed Single Point Grounding. 7.Secondary power shall be grounded to structure only once in each unit / experiment. 8.Cable shields shall be grounded to structure ground at both ends. Shields shall not be used as the return path for signal or power. 9.Non-magnetic materials shall be used wherever possible.The use of ferro-magnetics shall be avoided wherever possible. 10.It is recommended to use crystal oscillator controlled DC/DC converters Experimenter EMC requirements Develop the RPWI EMC requirements for the S/C by interaction during S/C design

Low Voltage Power Supply (LVPS) Göran Olsson Royal Institute of Technology (KTH) Space and Plasma Physics

LFA + AM +8V / -8V SCM PREAMP RWI Preamps RA-PWI Preamp LP-PWI Preamps 3.3V LVPS-A 1.8V 3.3V LVPS-B TBDLVPS CONTROL & MONITORING 1.8V 3.3V 1.8V +8V -8V DPU Clock, Control, Data and Emergency Power-Off, A + B CEB BACKPLANE SCM +8V / -8V 3.3V 1.8V LP-PWI +8V / -8V 3.3V 1.8V +8V / -8V 3.3V 1.8V RWI RA-PWI HFA LVPS IN RPWI JGO

Functional: DC power to all RPWI instruments: ±8V +3.3V, +1.8 V from V input, nominal total power output: ~10 W CEB Form Fit: PCB Dimensions 200x 150 x 1.6 mm Component height 12 mm upper side, 3 mm lower side Backplane connector 160 pin, 3 row Airborn WG series Mass 300 g Primary to secondary isolation Temperature range: -30 °C to +50 °C operating Redundant DC/DC converters and digital controllers TBD Power Switching: 5 instruments having two to four supply voltages Voltage and Current Monitoring Overcurrent Tripping; Limits under software control Temperature Monitoring: DC/DC converter and SCM sensor Performance: No-load Power (Including DC/DC converter, controller, monitoring and switches): 1.1 W Differential Efficiency: 82% Output Deviation: ±5% from nominal including all effects Output Ripple: < 5 mV rms LVPS Requirements

Controller B FPGA Voltage And Current Monitors (4) Power Switches (9 Instruments) Voltage and Current Monitors (24) 1.8, 3.3 V From SCM Thermistor From SC 28V CEB BPLN From SC 28V DPU 1.8, 3.3, ±8 V DC/DC Converter A 1.8, 3.3 V CDPU-A Ctrl: Clock, Command, Data, EPO DC/DC Converter B Housekeeping Controller A FPGA Common-Mode Filter Common-Mode Filter Redundant TBD DC/DC Converters and Controllers chained with the DPU Unused chain is a cold spare Common power bus for all instruments. Design to minimize risk of single point failures here. What if both chain A and B are powered? Must be survivable, but no functional requirement. - No mutual interlock implemented. Subject of further study. 1.8 V is regulated to 1.5 V locally on each subsystem Power switches have turn-on ramping Emergency Power-Off Common Bus LVPS Block Diagram

Main Transformer Synchronous Rectifiers Output Filters Primary to Secondary Isolation Double Shielding SecondaryPrimary Outputs: +1.8 V, 1.1 A +3.3 V, 1.1 A +8 V, 350 mA -8 V, 300 mA Input: V V DC EMI Filter Full-Wave Rectification No Feedback from Secondary LC Pi Filters Switchmode Regulator Controller Push-Pull Full-Wave 210 kHz Pulse-Width Modulator ‘Forward’ Converter 420 kHz Transformer Driver Regulated input voltage to Transformer Driver Current positive feedback: Counterbalances losses in driver transistors, transformer and rectifiers. First StageSecond Stage Shielded Two-stage Conversion: Excellent input and load regulation Low noise Low output cross-regulation Slightly lower efficiency mΩ Internal: ±15 V Inrush current limiter DC/DC Converter A/B

FPGA 3.3 V Linear Regulators: 1.5 V 2.5 V Power Switch Control (9) LVDS HK Control (ADC, Mux, Gain Switch) System clock derived from the CDPU interface clock: MHz If three consecutive samples (~15 ms) exceed the limit ► All voltages turned off for the affected instrument Housekeeping ADC Data CDPU A/B Instrument Power Control Housekeeping Control with Storage and Readout Overcurrent Tripping, limits under software control IVM: Actel ProASIC3 A3P250 FM: Actel RTSX72 DC/DC A/B Digital Controller A/B

1.DC/DC Converter, Housekeeping System and Stepper Motor Controller for EMMA, a plasma payload on the Swedish Astrid-2 satellite, launched December 10, Dimensions 177 x 134 x 16 mm. DC/DC design power 10 W. COTS components. This design has many features in common with the MMS LVPS. 2.DC/DC Converter for SPEDE, a plasma payload on the SMART-1 ESA Lunar Orbiter, launched Dimensions 71 x 44 x 11 mm. Design power is a mere 1.2 W. Impacted on the Moon as planned on September 3, Design Heritage LVPS IVM on the UNH lab bench with co- delivered dummy load board

Mass Circuit board Main Box Antennas/Sensors Width21cm meterg/m Depth15cm SCM650 Card mass/cm¨20.7 SCM Harness Number of cadrs6 Preamp100 Box mass1000g LP-PWI1800 Material density2.8 LP-PWI Harness Card mass1449g Preamp200 Box thickness4.7mm RWI1400 Box surface1191cm^2 RWI Harness Total Box Mass3000g RWI Preamp100 RA-PWI200 Harness mass1059g RA-PWI Harness84328 Preamp mass600g RA-PWI Preamp200 Sensor mass4050g Sensor + Box+Preamp7650g Total8709g

Scientists dream receiver A downgrade is needed for the JGO receivers. Low and high frequency analyzers Lennart Åhlen

TDA: Development of FPGA algorithms for digital analyzers to obtain high dynamic measurement range JGO Scientists dream receiver A downgrade is needed for the JGO receivers. Dynamic range: The ratio of the specified maximum signal level capability of a system to its noise level in a record of continues sampled data. What is required to fulfill the JGO since objective? Questions to be answered by the RPWI scientists. 1.Ranges and overlap for the low and high frequency receivers? 2.Wave-form capture? 3.Low and High frequency data coverage? 4.Number of parallel data channels? 5.Type of on-board data analyzes?

Low frequency receiver Signal processing: FFT, I/Q, Filter bank, Wavelets, PFT, Buffer memory for wave form capture and Burst data. Dynamic range: 80dB to 100Hz bandwidth High frequency receiver Burst data signal processing: FFT, I/Q, Filter bank, Wavelets, PFT, Buffer memory for wave form capture and Burst data. Dynamic range: 70dB to 10kHz bandwidth Measurement range: 70dB to 10kHz bandwidth Dynamic range: 70dB to 10kHz bandwidth

Under sampling high frequency receiver All high speed ADCs has a higher analog bandwidth than the maximum sampling rate. This makes it possible to build HF digital receivers by use of under-sampling. Under-sampling design approach is replacing mixer- based heterodyne receivers. Signal processing: FFT, I/Q, Filter bank, Wavelets, PFT, Principle of under sampling

Dual I/Q Mixer including SH Conventional mixer using high speed analog switches. Antenna impedance measurements Net work analyzer S11 type measurements Impedance antenna to plasma vs. frequency Useful for side-by-side antenna comparisons