Nina Drozd Supervisor: Fearghal Morgan Co-Supervisor: Martin Glavin Project Progress Presentation

Remote USB controlled lamp C:/Users/NUIG/Documents & Settings/Desktop/tg/fpgalab/fpgalab/ static/applets

Access system using riviera.nuigalway.ie server, add tunnels for proxy & sharkdog.nuigalway.ie Set up and log into compsoc account, then ssh into sharkdog (specific username needed), and ssh into Use tight VNC when desktop view of the system is needed, easier for developer use

System is of data- model-view architecture, in order to change anything in the system, all 3 components must be modified

Simple demos available for unregistered user, uploads defined bitstreams demo Redirects the user to register page demo Check user name against user database, check that password corresponds

CSR, SRAM read and write demo, last 3 CSR buttons used for testing, will be removed Virtual switches & buttons, when pressed, toggle pressed bit in dedicated CSR 9 and 8. Image processing, most functions work, problems with some Provide better support for online vhdl testing. Added virtual switch access, improved user interface, added VHDL sample project, need to package and create user guide

 Account creation needs to be revised  Yet to improve: ◦ Monitoring of all accounts by admin, know bitstream files uploaded, last login, etc. ◦ Query about vhdl or website use sent to admin using mail form ◦ User manual to create account and test bitstream files properly ◦ Admin has power over account creation, reg key requested from admin. ◦ Questionnaire used to improve website and system

 Tidy up the website  Registration: request reg. key from admin via form  Account management & statistics: ◦ Database files stored in..\fpgalab\sqlobject-history, need to add user_name as parameter in bitstreams database ◦ Bitstreams uploaded stored in fpgalab\uploads ◦ Unique session key for each user, need to assign to user_name and count sessions for user, after 5 sessions ask to fill out questionnaire, etc. ◦ If user inactive for e.g. 10 minutes, log off to allow access to others.  Package VHDL project (need to do function for each virtual switch), remove unused components (DSP just for demo)  Documentation: ◦ Basic system structure done, need to add details of file locations ◦ Guide for developer login into system (done) ◦ User guide (research done, creation in progress)