April 15, 20031 Synthesis of Signal Processing on FPGA Hongtao

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Presentation transcript:

April 15, Synthesis of Signal Processing on FPGA Hongtao

April 15, Getting started What is VLSI? ASIC family members Carrying on VHDL Synthesis structure Do it yourself Parallel ICA Re-configurable components

April 15, Development of VLSI Integrated Circuit (IC): A microelectronic semiconductor device consisting of many interconnected transistors and other components. ICs are fabricated (constructed) on a die (a small rectangle) cut from a silicon wafer. Containing logic gates: inverters, AND, OR, NAND, NOR, etc.

April 15, (continue) Small Scale Integration (SSI) -- tens transistors Medium Scale Integration (MSI) -- hundreds transistors Large Scale Integration (LSI) – thousands transistors Very Large-Scale Integrated Circuit (VLSI) has hundreds of thousands. One megabyte RAM contains more than one million transistors, developed in 1986 Wafer-scale integration The most extreme technique. Using whole uncut wafers as components.

April 15, ASIC Family ASIC PLD FPGA MGA Standard Library Cells Analog / Digital Mixed Technologies Full-Custom Semi-Custom Programmable Non-programmable PLD: programmable logic device MGA: mask gate array

April 15, FPGA v.s. PLD FPGA Best for low quantity applications Vendor prefabricates rows of gates and programmable connections User specifies connections to implement logic functions Replaces 2,000 to 2,000,000 gates Implementation time: within hours Development system cost: $5,000 – 10,000 (PC-based) PLD Best for simple design Vendor prefabricates multiple sets of gates with programmable connections User specifies connections to implement logic functions Replaces 300 to 8,000 gates Implementation time: within minutes Development system cost: $3,000 – 5,000 (PC-based)

April 15, MGA and Standard Library Cells MGA Best for moderate-sized designs Vendor prefabricates rows of gates and wafers User specifies two layers to implement logic functions Replaces 10,000 to 10,000,000 gates After place & route, masks are made for two layers Development system cost: $ 50K (Workstation-based) Turnaround time for prototypes: weeks Standard Library Cells Best for high quantity applications with multiple functions, such as CPU and RAM. User selects cells and specifies two layers of interconnections. Replaces 100,000 to 10,000,000 gates After place & route, masks are made for all layers Development system cost: $100K (Workstation-based) Turnaround time for prototypes: 8 weeks

April 15, FPGA Features Advantages Rapid prototyping Low risk Low testing costs Standard product advantages Life cycle, reusable Disadvantages Chip capacity and cost Speed of circuit

April 15, Getting started What is VLSI? ASIC family members Carrying on VHDL Synthesis structure Do it yourself Parallel ICA Re-configurable components

April 15, VHDL Hardware Description Language (HDL). VHDL: VHSIC (Very High Speed Integrated Circuit) Hardware Description Language. Developed to standardize documentation for maintenance and possible redesign, by DOD. IEEE VHDL standard approved in Verilog: Developed for verification of logic, by Gateway Automation.

April 15, sorting:PROCESS(clock) BEGIN if clock'event and clock='1' then if all_ic_input_ok='1' and all_ic_output_ok='0' then …… if sort_weight(loop_count+1) >= sort_weight(loop_count) then temp1 <= sort_weight(loop_count); sort_weight(loop_count) <= sort_weight(loop_count+1); sort_weight(loop_count+1) <= temp1; temp2 <= sort_band(loop_count); sort_band(loop_count) <= sort_band(loop_count+1); sort_band(loop_count+1) <= temp2; change <= '1'; change_count <= loop_count+1; end if; loop_count <= loop_count + 1; end if; if loop_count = band-2 then loop_count <= 0; sort_count <= sort_count + 1; end if; if sort_count=band-1 then all_ic_output_ok <= '1'; end if; …… END PROCESS sorting; Example: Comparing

April 15, Synthesis structure

April 15, Getting started What is VLSI? ASIC family members Carrying on VHDL Synthesis structure Do it yourself Parallel ICA Re-configurable components

April 15, Parallel ICA Diagram

April 15, Synthesis Structure

April 15, Structure of Component OneUnit Loop until Converge Normalize Initialize Weight Vector Update Compute

April 15, Structure of Component Decorrelation Loop until Converge Normalize Independent Component Input Update Decorrelate

April 15, Structure of Component Comparing

April 15, Coverage of Re-configurable Components

April 15, Pre-layout Simulations Components: One-unit Decorrelation Comparing Top level

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April 15, Layout Simulation Xilinx Virtex 1000EHQ240 Estimating 4 Independent Components 92% utilization

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April 15, Post-layout Simulation

April 15, Design and FPGA Capacity

April 15,

April 15, Conclusion FPGA is an efficient solution for signal processing.

April 15, Reference Deniel D. Gajdki and Loganath Ramachandran. Introduction to high-level synthesis. IEEE Design and Test of Computers, pages 44–54, Don Bouldin. ECE 551: Designing application-specific integrated circuits, Fall Don Bouldin. Design of Systems on a Chip, chapter Synthesis of FPGAs and Testable ASICs. Kluwer Academic Press, Habib Youssef Sadiq M. Sait. VLSI Physical Design Automation, Theory and Practice. World Scientific Publishing Company, June 1999.