Outline Decoder Encoder Mux. Decoder Accepts a value and decodes it Output corresponds to value of n inputs Consists of: Inputs (n) Outputs (2 n, numbered.

Slides:



Advertisements
Similar presentations
ECE 2110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices Encoders.
Advertisements

Combinational Circuits
Decoders/DeMUXs CS370 – Spring Decoder: single data input, n control inputs, 2 outputs control inputs (called select S) represent Binary index of.
System Digital Encoder, Decoder, and Contoh Penerapanya.
Combinational Logic Building Blocks
EE2174: Digital Logic and Lab
DIGITAL SYSTEMS TCE OTHER COMBINATIONAL LOGIC CIRCUITS DECODERS ENCODERS.
ECE 331 – Digital System Design
Multiplexer MUX. 2 Multiplexer Multiplexer (Selector)  2 n data inputs,  n control inputs,  1 output  Used to connect 2 n points to a single point.
Any logic circuits can be transformed to an implementation where only NAND gates (and inverters) are used. The general approach to finding a NAND-gate.
Chapter2 Digital Components Dr. Bernard Chen Ph.D. University of Central Arkansas Spring 2009.
 Combinational circuit that selects binary information from one of many input lines and directs information to a single output line.
ETE Digital Electronics Multiplexers, Decoders and Encoders [Lecture:10] Instructor: Sajib Roy Lecturer, ETE, ULAB.
Combinational Logic Chapter 4.
CS 151: Digital Design Chapter 3 3-8: Encoding. CS 151 Encoding Encoding - the opposite of decoding - the conversion of a maximum of 2 n input code to.
Combinational Logic Design
Sahar Mosleh PageCalifornia State University San Marcos 1 Multiplexer, Decoder and Circuit Designing.
Combinational Circuit – Arithmetic Circuit
1 Digital Logic Design Week 7 Decoders, encoders and multiplexers.
CS2100 Computer Organisation MSI Components (AY2015/6 Semester 1)
WEEK #9 FUNCTIONS OF COMBINATIONAL LOGIC (DECODERS & MUX EXPANSION)
Digital Logic Problems (II) Prof. Sin-Min Lee Department of Mathematics and Computer Science.
Combinational Design, Part 3: Functional Blocks
Logical Circuit Design Week 6,7: Logic Design of Combinational Circuits Mentor Hamiti, MSc Office ,
Multiplexers and Demultiplexers, and Encoders and Decoders
Morgan Kaufmann Publishers
Decoders, Encoders, Multiplexers
CS 105 DIGITAL LOGIC DESIGN Chapter 4 Combinational Logic 1.
CS151 Introduction to Digital Design
Computer Science 210 Computer Organization Control Circuits Decoders and Multiplexers.
CO UNIT-I. 2 Multiplexers: A multiplexer selects information from an input line and directs the information to an output line A typical multiplexer has.
Combinational Circuits by Dr. Amin Danial Asham. References  Digital Design 5 th Edition, Morris Mano.
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Lecture 7 Dr. Shi Dept. of Electrical and Computer Engineering.
Chapter Four Combinational Logic 1. Discrete quantities of information are represented in digital systems by binary codes. A binary code of n bits is.
Magnitude Comparator A magnitude comparator is a combinational circuit that compares two numbers, A and B, and then determines their relative magnitudes.
Magnitude Comparator Dr. Ahmed Telba.
Combinational Circuit Design. Digital Circuits Combinational CircuitsSequential Circuits Output is determined by current values of inputs only. Output.
Chapter 3: Combinational Functions and Circuits 3-5 to 3-7: Decoders
Module 11.  In Module 9, we have been introduced to the concept of combinational logic circuits through the examples of binary adders.  Meanwhile, in.
Digital System Design Multiplexers and Demultiplexers, and Encoders and Decoders.
CS151 Introduction to Digital Design Chapter 3: Combinational Logic Design 3-5 Combinational Functional Blocks 3-6 Rudimentary Logic Functions 3-7 Decoding.
ECE 2110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices Multiplexers.
XYZCS Designing Binary Adders with decoders C(X,Y,Z) =  m(3,5,6,7) S(X,Y,Z) = S m(1,2,4,7);
MSI Combinational logic circuits
Digital Design Module 2 Decoder Amit Kumar AP SCSE, GU Greater Noida.
Combinational Circuits. Outline Boolean Algebra Decoder Encoder MUX.
1 DLD Lecture 16 More Multiplexers, Encoders and Decoders.
Multiplexer (MUX) A multiplexer can use addressing bits to select one of several input bits to be the output. A selector chooses a single data input and.
Digital Design Module 2 Multiplexer and Demultiplexer
DIGITAL COMPONENTS. MULTIPLEXERS A multiplexer is a combinational circuit that receives binary information from one of 2 n input data lines and directs.
Chapter4: Combinational Logic Part 4 Originally By Reham S. Al-Majed Imam Muhammad Bin Saud University.
Multiplexer.
MSI Circuits.
Combinational Circuits
CS221: Digital Logic Design Combinational Circuits 3
Combinational Circuits
Multiplexers and Demultiplexers,
Combinational Logic Circuits
Combinational Circuit Design
NAND-ONLY LOGIC CIRCUITS
Magnitude Comparator A magnitude comparator is a combinational circuit that compares two numbers, A and B, and then determines their relative magnitudes.
CSCE 211: Digital Logic Design
CSCE 211: Digital Logic Design
COE 202: Digital Logic Design Combinational Circuits Part 3
Multiplexers Anindya IE CSE.
CSCE 211: Digital Logic Design
CSCE 211: Digital Logic Design
Digital System Design Combinational Logic
Multiplexers Mux.
Presentation transcript:

Outline Decoder Encoder Mux

Decoder Accepts a value and decodes it Output corresponds to value of n inputs Consists of: Inputs (n) Outputs (2 n, numbered from 0  2 n - 1) Selectors / Enable (active high or active low)

The truth table of 2-to-4 Decoder

2-to-4 Decoder

The truth table of 3-to-8 Decoder A2A1A0D0D1D2D3D4D5D6D

3-to-8 Decoder

3-to-8 Decoder with Enable

Decoder Expansion Decoder expansion Combine two or more small decoders with enable inputs to form a larger decoder 3-to-8-line decoder constructed from two 2-to-4-line decoders The MSB is connected to the enable inputs if A 2 =0, upper is enabled; if A 2 =1, lower is enabled.

Decoder Expansion

Combining two 2-4 decoders to form one 3-8 decoder using enable switch The highest bit is used for the enables

How about 4-16 decoder Use how many 3-8 decoder? Use how many 2-4 decoder?

Outline Decoder Encoder Mux

Encoders Perform the inverse operation of a decoder 2 n (or less) input lines and n output lines

Encoders

Encoders with OR gates

Encoders Perform the inverse operation of a decoder 2 n (or less) input lines and n output lines

Accepts multiple values and encodes them Works when more than one input is active Consists of: Inputs (2 n ) Outputs when more than one output is active, sets output to correspond to highest input V (indicates whether any of the inputs are active) Selectors / Enable (active high or active low) Priority Encoder

D3D2D1D0A1A2V 0000xX

Priority Encoder

Outline Decoder Encoder Mux

Multiplexer (MUX) A selector chooses a single data input and passes it to the MUX output It has one output selected at a time. A multiplexer can use addressing bits to select one of several input bits to be the output.

4 to 1 line multiplexer S1S1 S0S0 F 00I0 01I1 10I2 11I3 4 to 1 line multiplexer 2 n MUX to 1 n for this MUX is 2 This means 2 selection lines s 0 and s 1

Multiplexer (MUX) Consists of: Inputs (multiple)= 2 n Output (single) Selectors (# depends on # of inputs) = n Enable (active high or active low)

Function table with enable

Multiplexers versus decoders A Multiplexer uses n binary select bits to choose from a maximum of 2 n unique input lines. Multiplexers and decoders both can decode minterms. Decoders have n number of output lines while multiplexers have only one output line. The decoded minterms are used to select data from one of up to 2n unique data input lines. The output of the multiplexer is the data input whose index is specified by the n bit code.

Multiplexer Versus Decoder Note that the multiplexer has an extra OR gate. A1 and A0 are the two inputs in decoder. There are four inputs plus two selecs in multiplexer. 4-to-1 Multiplexer 2-t0-4 Decoder

Cascading multiplexers Using three 2-1 MUX to make one 4-1 MUX S1S1 S0S0 F 00I0 01I1 10I2 11I3 F

F 2-1 MUX S E S 2 E S2S2 S1S1 S0S0 F 000I0I0 001I1I1 010I2I2 011I3I3 100I4I4 101I5I5 110I6I6 111I7I7 I0I1I0I1 I2I3I2I3 I4I5I4I5 I6I7I6I7 Example: Construct an 8-to-1 multiplexer using 2-to-1 multiplexers.

Example ( ) Construct 8-to-1 multiplexer using one 2-to-1 multiplexer and two 4-to-1 multiplexers S2S2 S1S1 S0S0 X

Quadruple 2-to-1 Line Multiplexer Used to supply four bits to the output. In this case two inputs four bits each.

Quadruple 2-to-1 Line Multiplexer E (Enable) S (Select) Y (Output) 0XAll 0’s 10A 11B