MODERN Final Review ENIAC MODERN Ref. Technical Annex MODERN_PartB Rev2 v3.8 WP1: Giuliana GangemiWP2: André Juge WP3: Wilmar HeuvelmanWP4: Davide Pandini WP5: Loris Vendrame Coordinator: Jan van Gerwen Date: May 3 rd, 2012

CONFIDENTIAL MODERN Final Review May 3rd, 2012 Agenda (1) Welcome General information (Jan) –Objectives –Consortium –Amendments –Resources planned and used –Overview of deliverables and milestones status –Dissemination and exploitation –Relationship between workpackages –Other issues, Q&A For WP1 (Giuliana), WP2 (André), WP3 (Wilmar) and WP4 (Davide) –Link with other WPs and Tasks –Progress, highlights and lowlights –Technical status and achievements of deliverables (incl. changes) –Cooperation –Dissemination (publications, patents), exploitation –Other issues, Q&A 2

CONFIDENTIAL Agenda (2) For WP5 (Loris and others) –Deliverables (incl. changes) –Demonstrator goals w.r.t. related project tasks –Major achievements, highlights / lowlights and comparison w.r.t. state of the art –Demo’s and technical highlights: Thales: Philippe Millet / Simon Heywood “License plate detection implementation on FPGA of robust parallel computing architecture ” UNBO / STI: Davide Rossi “Design flow validation for via/metal programmable gate arrays” Tiempo: Marc Renaudin UPC: Francesc Moll Echeto IFXA/IMCA: Michael Fulde LETI: Edith Beigne AMS: Alexander Steinmar –Q&A MODERN Final Review May 3rd,

CONFIDENTIAL MODERN Final Review May 3rd, 2012 Objectives The objective of the MODERN project is to develop new paradigms in integrated circuit design that will enable the manufacturing of reliable, low cost, low EMI, high-yield complex products using unreliable and variable devices. Specifically, the main goals of the project are:  Advanced, yet accurate, models of process variations for nanometre devices, circuits and complex architectures.  Effective methods for evaluating the impact of process variations on manufacturability, design reliability and circuit performance. oReliability, noise, EMC/EMI. oTiming, power and yield.  Design methods and tools to mitigate or tolerate the effects of process variations on those quantities applicable at the device, circuit and architectural levels.  Validation of the modelling and design methods and tools on a variety of silicon demonstrators. Layout and strain induced variability (Synopsys) 4

CONFIDENTIAL MODERN Final Review May 3rd, 2012 Consortium The MODERN Consortium features strong competence and expertise in the field of advanced technologies, with a well-balanced participation between Large Industries, SMEs, Research Centres and Universities from all over Europe. 5

CONFIDENTIAL MODERN Final Review May 3rd, 2012 Amendments 1. The change of project coordinator from ST to NXP and ST-Crolles being replaced by ST- Grenoble 2. The removal of some inconsistencies between some deliverables 3. The subcontracting of work by Glasgow to GSS Ltd. 4. CSEM withdraws due to lack of national funding as of To account for the leaving of some NXP employees and a related change in direction of the NXP PDM group the deliverables D5.3.2 and D5.3.3 are (slightly) changed 6. To account for some technical difficulties encountered in the research activities within ST-I Tasks 3.1, 3.4 and 5.3 are (slightly) changed 7. Change of Deliverables D2.2.6, D2.3.4, D2.2.4, D2.5.3 and correction of text in “ Deliverables list”. 8. Rephrasing of D4.3.4 and changing the relative weight accordingly from WP4 to WP3. 9. The Spanish partner Elastic Clocks S.L. (ELX, partner #4) withdraws from the project due to dissolution of the parent company. 10. Due to a lack of human resources at the Graz University of Technology (TUGI) the contribution of TUGI to Task 5.2 is reduced. 11. In order to facilitate the preparation of the Final Review to move the end date of the project from February 29 th to May 4 th, Partner #6 Infineon Technologies Austria AG is replaced by Intel Mobile Communications Austria due to the takeover by Intel. 6

CONFIDENTIAL MODERN Final Review May 3rd, 2012 Resources planned and used 7

CONFIDENTIAL MODERN Final Review May 3rd, 2012 Overview of deliverables and milestones status (1) Deliverables due >M22 8

CONFIDENTIAL MODERN Final Review May 3rd, 2012 Overview of deliverables and milestones status (1) Deliverables due >M22 9

CONFIDENTIAL MODERN Final Review May 3rd, 2012 Overview of deliverables and milestones status (1) Deliverables due >M22 10

CONFIDENTIAL MODERN Final Review May 3rd, 2012 Overview of deliverables and milestones status (2) Milestones due >M22 11

CONFIDENTIAL MODERN Final Review May 3rd, 2012 Overview of deliverables and milestones status (3) Conclusion: All project Deliverables and Milestones are ready Deliverable D5.2.3: Few partners are waiting for silicon (LETI and TIEMPO 32nm) so their sections contains the characterization plan and the simulated targets rather than the experimental evidence. This will be updated as soon as available D Final Report: Awaiting data from some partners 12

CONFIDENTIAL MODERN Final Review May 3rd, 2012 Dissemination and exploitation MODERN participated in the Poster & Demo Session at European Nanoelectronics Forum 2011 in Dublin, Ireland. Most partners have contributed and attended to the annual European VARI workshops on CMOS Variability On October 6 th and 7 th 2011 the ‘International Workshop on Simulation and Modeling of Memory devices’ was organized in Agrate which was attended by 58 persons. A Workshop at DATE’12 with the theme ‘Variability modelling and mitigation in current and future technologies (VAMM2012)’ is organized. This workshop is a co-operation of the projects ‘Synaptic’, ‘TRAMS’ and MODERN. The public and the internal part of the MODERN web-site are and will be updated regularly.MODERN web-site The publications are listed in the progress reports of the WPs in chapter 3. The actual list of publications with over 103 titles is available from the section ‘papers’ on the MODERN website.section ‘papers’ on the MODERN website 13

CONFIDENTIAL MODERN Final Review May 3rd, 2012 Relationship between workpackages 14

CONFIDENTIAL MODERN Final Review May 3rd, 2012 Other issues Q&A ? 15

CONFIDENTIAL WP1 agenda Link with other WPs and Tasks Progress, highlights and lowlights Technical status and achievements of deliverables (incl. changes) Cooperation Dissemination (publications, patents), exploitation Other issues, Q&A MODERN Final Review May 3rd,

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CONFIDENTIAL WP2 agenda Link with other WPs and Tasks Progress, highlights and lowlights Technical status and achievements of deliverables (incl. changes) Cooperation Dissemination (publications, patents), exploitation Other issues, Q&A 18 MODERN Final Review May 3rd, 2012

CONFIDENTIAL 19 MODERN Final Review May 3rd, 2012

CONFIDENTIAL WP3 agenda Link with other WPs and Tasks Progress, highlights and lowlights Technical status and achievements of deliverables (incl. changes) Cooperation Dissemination (publications, patents), exploitation Other issues, Q&A 20 MODERN Final Review May 3rd, 2012

CONFIDENTIAL 21 MODERN Final Review May 3rd, 2012

CONFIDENTIAL WP4: Outline Link with other WPs and Tasks Progress, highlights and lowlights Technical status and achievements of deliverables (incl. changes) Cooperation Dissemination (publications, patents), exploitation Other issues, Q&A 22 MODERN Final Review May 3rd, 2012

CONFIDENTIAL 23 MODERN Final Review May 3rd, 2012

CONFIDENTIAL WP5 agenda Deliverables (incl. changes) Demonstrator goals w.r.t. related project tasks Major achievements, highlights / lowlights and comparison w.r.t. state of the art Demo’s and technical highlights: –Thales: Philippe Millet / Simon Heywood “License plate detection implementation on FPGA of robust parallel computing architecture ” –UNBO / STI: Davide Rossi “Design flow validation for via/metal programmable gate arrays” –Tiempo: Marc Renaudin –UPC: Francesc Moll Echeto –IFXA/IMCA: Michael Fulde –LETI: Edith Beigne –AMS: Alexander Steinmar Q&A 24 MODERN Final Review May 3rd, 2012

CONFIDENTIAL DELIVERABLES D5.1.3: TUGI, AMS, NMX, STF2 “PV statistical data analysis coming from standard and improved test structures in different technologies” D5.2.3: TMPO, UPC, NXP, IFXA, LETI, “test chip characterization (evaluation to show effectiveness of PVT circuitry, of basic processing circuits implemented with regular layouts,), calibration of PV robust analysis flows” In Amendment n. 10 TUGI activity has been carved out D5.3.3: ST-I, THL, NXP “Trial PDKs (by ST-I), application programming on robust parallel architectures. Software prototype implementation of parameterized design methodology and MOR for statistical parameter variations” Milestone M5.2 ‘Demonstrator final results’ passed 25 MODERN Final Review May 3rd, 2012

CONFIDENTIAL Demonstrator goals w.r.t. related project tasks Logic CMOS Tech. nodes: 65, 40, 32nm RF / AMS Tech. nodes: 65, 32, 28nm Reliability Aging Noise Performance Robustness Monitoring (T3.3) Redundancy (T3.3) Adaptation (T4.1) Regularity (T4.4) HW & SW Robust architectures (T4.5) HW & SW Monitor & Control (T3.3)

CONFIDENTIAL RESULTS T5.1 OWNERNODE (nm) CONTENT Highlights / Lowlights Majors achievementsComparison w.r.t. state of the art NMX / Micron NVMCombined mismatch test structures + Works fine - Not tested yet on aggressive CMOS Poly dummy analysisDecoupling among poly CD and implant overlap (*) AMSPowerKelvin RON probe; Matching multiplexer + Functional + Mismatch vs spacing Improved accuracy and repeatability; Ok w.r.t. standard structures, Applied to power devices ST-FLogicKelvin mismatch measurements - Gain measures not clear Accuracy for mean values Trade off: accuracy vs. complex and long e-test 27 MODERN Final Review May 3rd, 2012 (*) L. Bortesi, L. Vendrame, G. Fontana, “Combined test structure for systematic and stochastic Mosfets and gate resistance process variation assessment”, IEEE Conference on Microelectronics Test Structures, March 2010, pp

CONFIDENTIAL RESULTS T OWNERNODE (nm) CONTENT Highlights / Lowlights Majors achievementsComparison w.r.t. state of the art IFXA IMCA 32M&C: OPA and VCO + Works as intendedDegradation measured 1st time for 32nm analog and RF building blocks Building blocks are “state-of-the-art” but aging new characterization methods introduced IFXA IMCA 32M&C: SAR-ADC + Works as intendedError correction for aging in ADC proven on silicon Nothing comparable published for ADCs IFXA IMCA 32M&C: burn in, chopping, auto- zeroing + All structures and modes functional; - Autozeroing still in Lab M&C methods proven on silicon Nothing comparable published for analog/mixed-signal IFXA IMCA 28DCDC converter and matching + All structures and modes functional; - no degradation due to hard-failures Digital DCDC in 28nm with good efficiency 1 st DCDC in 28nm TMPO 32Variability Tolerant Asynchronous microcontroller + Design and fabrication of a fully delay insensitive digital sub-system - fabrication delay Robust, variability- tolerant clock-less delay- insensitive circuits and associated CAD flow Unique CAD flow enabling the fabrication of standard cell based delay insensitive circuits 28 MODERN Final Review May 3rd, 2012

CONFIDENTIAL RESULTS T OWNERNODE (nm) CONTENT Highlights / Lowlights Majors achievementsComparison w.r.t. state of the art UPC40VCDL with regular structures evaluation of lithography-induced variations using a regular fabric proposal (VCTA). Measurements not finished yet. Preliminary results confirm a measurable difference in the variability of FC w.r.t. regular VCTA chains Measurements not finished yet. UPC65LNA with M&CThermal monitoring of RF figures of merit like gain. demonstrated, Novel technique to embed analogue / RF circuits in feedback loops using temperature as observable Novel idea for non- invasive monitoring and healing. Comparison can only be made with electrical invasive techniques. UPC65Adjustable VCO and ILFD - results partially differs from simulations, due to a bug in the EM inductors modelling (underestimation). Operation principle and the optimization trade- offs involving power consumption, tuning and locking ranges of the selected ILFD topology. The measurements did not meet the expected requirements. 29 MODERN Final Review May 3rd, 2012

CONFIDENTIAL RESULTS T OWNERNODE (nm) CONTENT Highlights / Lowlights Majors achievementsComparison w.r.t. state of the art LETI32Adaptive Voltage and frequency scaling fine- grain processor cluster Design of a fully dynamically adaptive architecture at fine- grain using other WP developments Full design and verification flow for this mixed-signal complex SoC Compared to existing techniques, fine-grain is the solution to face in-die process variations. THALESFPGARobust parallel computing architecture + multicore on FPGA based on microBlaze processors linked with a NoC capable of reconfiguring itself after simulated hardware failure of a core. - simpler application than first targeted. A license plate detection application on a 16 cores architecture. 10 cores are actually used, 1 is a supervisor, 5 remains for reconfiguration purpose. After hardware failure of a core, the system reconfigures itself and starts again. Approach of reconfiguring the multicore after failure by doing task migration. Several projects are in this direction like ADAM (french ANR), Recomp (Artemis) or Flextiles (FP7). 30 MODERN Final Review May 3rd, 2012

CONFIDENTIAL RESULTS T OWNERNODE (nm) CONTENT Highlights / Lowlights Majors achievementsComparison w.r.t. state of the art NXP65production based test chip for substrate noise modeling verification: Test chip B (CLN65 design) -Measurements didn’t show the expected improvement in digital noise interference, while using “clean” well biasing connections. The root-cause is being investigated Various substrate isolation methodologies implemented on production design NXP140production based test chip for substrate noise modeling verification: (CMOS14) - the first silicon results cannot provide any insights into the circuit behaviour. Substrate noise sensor implemented in production design 31 MODERN Final Review May 3rd, 2012

CONFIDENTIAL RESULTS T5.3 OWNERNODE (nm) CONTENT Highlights / Lowlights Majors achievementsComparison w.r.t. state of the art THALES-SW implentation of the “licence plate detection” Designed at SystemC simulator level Works fine on the FPGA implementation See note in T5.2 ST-I-Trial PDKUsability ST-I-SOC design flow of via/metal programmable gate array functionalVerification successfulFabric usability NXP-Model Order Reduction and parametrized design MORE used by partners (NMX/Micron) Increased automation and usability Steps toward analogue synthesis SNPS-Various implementation (see T2.2) Results quality verified on same templates with different tools and methods Enhancement of tool performance and usability 32 MODERN Final Review May 3rd, 2012

CONFIDENTIAL …in summary 11 test chips –9 Silicon available (6 confirm the expectations, 3 require additional investigations) –2 waiting for results 1 FPGA successful implementation –HW &SW fully functional –Practical example of a final application 3 SW / flows prototypes and a commercial SW enhancement test structures revised and further improved with a trade-off among test time / accuracy / complexity / silicon area 33 MODERN Final Review May 3rd, 2012

CONFIDENTIAL WP5 Demos and Technical highlights Demo’s and technical highlights: –Thales: Philippe Millet / Simon Heywood “License plate detection implementation on FPGA of robust parallel computing architecture ” –UNBO / STI: Davide Rossi “Design flow validation for via/metal programmable gate arrays” –Tiempo: Marc Renaudin –UPC: Francesc Moll Echeto –IFXA/IMCA Michael Fulde –LETI: Edith Beigne –AMS: Alexander Steinmar 34 MODERN 2010 Review March 1st, 2011

CONFIDENTIAL THALES - DEMO 35 MODERN Final Review May 3rd, 2012

CONFIDENTIAL UNBO ST- I - DEMO 36 MODERN Final Review May 3rd, 2012

CONFIDENTIAL IFXA/IMCA 37 MODERN Final Review May 3rd, 2012

CONFIDENTIAL UPC 38 MODERN Final Review May 3rd, 2012

CONFIDENTIAL AMS 39 MODERN Final Review May 3rd, 2012

CONFIDENTIAL LETI 40 MODERN Final Review May 3rd, 2012

CONFIDENTIAL TIEMPO Work Demonstrate variability-tolerant circuit design – Delay insensitivity = correct independently of actual delays – Design flow – Test-chip fabrication using STMicroelectronics 32 nm process – Test-chip characterization Collaboration with STMicroelectronics and Leti COPYRIGHT TIEMPO S.A.S – 2012 – Do not copy/forward without prior written approval from TIEMPO

CONFIDENTIAL Test-chip Fully asynchronous Fully digital About 500 Kgates Use of a small set of asynchronous cells (13 functions, 50 layouts) compliant with the standard cell library 48 pin QFN package Taped-out in July 2011 Packaged silicon expected beginning of May (delayed) COPYRIGHT TIEMPO S.A.S – 2012 – Do not copy/forward without prior written approval from TIEMPO TAM16 µC RAM GPIO ROM Serial_In/Out RS232 Decoder TIEMPO Test-Chip STMicroelectronics 32nm process

CONFIDENTIAL Design flow applied Cells design (coll. Leti) Cells characterization Synthesis using ACC Validation Place and Route (coll. STM) Validation No timing closure Only 2 constraints - Max cap - Max transition Focus on physical verifications ACC synthesis Standard cells Asynch cells P&R SystemVerilog / SDC Verilog SDC / SDF Simulation SystemVerilog Benches Tape-Out Physical verifications COPYRIGHT TIEMPO S.A.S – 2012 – Do not copy/forward without prior written approval from TIEMPO

CONFIDENTIAL Test-chip characterization Test-board development – Power supplies, Host interface, PIOs Test programs – Microcontroller BIST – ROM check – RAM read/write test – RS232 test and echo mode – Instruction loops – Loader to execute specific test programs All these test programs provide an output status on the PIOs COPYRIGHT TIEMPO S.A.S – 2012 – Do not copy/forward without prior written approval from TIEMPO

CONFIDENTIAL Test-chip characterization COPYRIGHT TIEMPO S.A.S – 2012 – Do not copy/forward without prior written approval from TIEMPO Functionally-guaranteed test chips automatically deliver process-related timing information at their primary outputs Characterization corner 1 Characterization corner 2 Characterization corner 3 Chips should be back early May About 30 packaged circuits, 10 per wafer (slow, typical, fast) Test and characterize speed and power w.r.t –Process conditions –Locations on the wafer –Operating voltages –Test programs Scheduled by mid-June 2012

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CONFIDENTIAL MODERN Final Review May 3rd,