Analog Layout.

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Presentation transcript:

Analog Layout

Analog Layout MOSFET Layout layout example (with schematic):

Analog Layout CMOS Passive Elements Poly1-poly2 capacitor structure

Analog Layout CMOS Passive Elements Parasitics associated with the poly1-poly2 capacitor structure

Analog Layout CMOS Passive Elements Careful layout can reduce parasitic resistance associated with cap structure

Analog Layout CMOS Passive Elements Additional options for implementing capacitors in CMOS technology include: metal1-metal2 capacitors MOS caps (drain shorted to source MOSFET operating in SI) n+ or p+ diffusions to well or substrate Well-to-substrate

Analog Layout CMOS Passive Elements Good analog design utilizes ratioing of components:

Analog Layout CMOS Passive Elements Guard ring components to isolate them from substrate noise:

Analog Layout CMOS Passive Elements Good example of layout of matched elements (R1 & R2): consistent orientation (horizontal in this case) consistent parasitics don’t forget to guard ring!

Analog Layout CMOS Passive Elements Common-centroid layout improves element matching (at the expense of uneven parasitics between the elements): in Fig. 7.7(a), RA = ‘16’ and RB = ‘20’ in Fig. 7.7(b), RA = ‘18’ and RB = ‘18’

Analog Layout Common-centroid structure for four elements (resistors, MOSFETs, or capacitors):

Analog Layout Also use dummy elements to improve matching:

Analog Layout Beware of poly under etching in layout of capacitor unit cells! Circular poly structures guarantee consistent under etching:

Analog Layout Good layout practices for analog circuits: Use gate lengths several times larger than the technology’s minimum gate length if all possible. This helps reduces  effects while improving matching. Use multiple source/drain contacts along the width of the transistor to reduce parasitic resistance and provides evenly distributed current through the device.

Analog Layout Good layout practices for analog circuits (continued): Interdigitize large aspect ratio devices to reduce source/drain depletion capacitance. Using an even number (n) of gate fingers can reduce Cdb, Csb by one-half or (n + 2)/2n depending on source/drain designation. Typically it is preferred to reduce drain capacitance more so than source capacitance. Also use dummy poly strips to minimize mismatch induced by etch undercutting during fab.

Analog Layout Good layout practices for analog circuits (continued): Matched devices should have identical orientation. An example of what not to do is shown below.

Analog Layout Good layout practices for analog circuits (continued): Interdigitization can be used in a multiple transistor circuit layout to distribute process gradients across the circuit. This improves matching. Use common-centroid structures.

Analog Layout Matching Errors in MOSFET Current Mirrors: Good layout design is essential for circuits needing matched devices. Layout techniques are effectively used to minimize first-order mismatch errors due to variations in these process parameters: gate-oxide thickness, lateral diffusion, oxide encroachment, and oxide charge density.

Analog Layout Matching Errors in MOSFET Current Mirrors (continued): Considering only the effects of threshold voltage mismatch within the simple current mirror, its current ratio is described by for SI saturation operation if a symmetric distribution in threshold voltage across the circuit is assumed (i.e., VTHN1 = VTHN  0.5VTHN and VTHN2 = VTHN + 0.5VTHN). Note the dependence on VGS. A reduction in VGS increases the input/output error in current mirrors induced by threshold voltage mismatch.

Analog Layout Matching Errors in MOSFET Current Mirrors (continued): Considering only transconductance parameter mismatch, where the value of KPn is the average transconductance parameter between the two transistors within the simple current mirror. Considering only VDS and  effects [SI sat.] , These, too, can be a significant source of error (e.g., 11%! if VDS1 = 2V, VDS2 = 4V, (c + m)1 = 0.04V-1, and (c + m)1 = 0.05V-1).