Manoj Chacko Director Product Management Signoff Summit November 21, 2003 Physical Signoff with Cadence PVS

2© 2013 Cadence Design Systems, Inc. All rights reserved. Cadence Physical Verification System Increasing Foundry Coverage from 180nm down to 16/14N FF Comprehensive Integration with Virtuoso, Encounter, & QRC Advanced Node, DFM, SiP/3D-IC Integrations 100+ companies switched to PVS in past 24 months Drivers: Alternative to Calibre, in-design signoff, adv. node, mixed signal 100+ companies switched to PVS in past 24 months Drivers: Alternative to Calibre, in-design signoff, adv. node, mixed signal In-Design, and Full Chip Signoff

3© 2013 Cadence Design Systems, Inc. All rights reserved. Wide Foundry Coverage PVS Rule Deck Availability TSMC 180, 65, 55, 45, 40, 28nm, 20nm, 16nm decks available GF 180nm, 130nm, 65nm and 40nm: available; 28nm, 20nm, and 14nm: ongoing. ST 20nm, B9mw, H9A, B7RF, 28FDSOI, 14FDSOI IBM 14nm: ongoing SAMSUNG 20nm, 28nm and14nm: ongoing SMIC 40nm, 28nm, 20nm, 14nm: ongoing UMC 130nm, 110nm, 65nm and 45nm XFAB XH018, XH035, XA035: available online; other process nodes: per request AMS C35: available online; 2H2013: H35 Huali 55nm: available online

4© 2013 Cadence Design Systems, Inc. All rights reserved. Adopting to PVS as Golden Signoff 65nm - 28nm

5© 2013 Cadence Design Systems, Inc. All rights reserved. PRESS RELEASE Source: Presented at CDNLive2013, (

6© 2013 Cadence Design Systems, Inc. All rights reserved. IBM SAMSUNG QUALCOMM KLA TENCOR FUJITSU NXP HITACHI JAPAN DISPLAY STMICROELECTRONICS RENESAS ELECTRONICS HITTITE MICROWAVE SHARP RESEARCH IN MOTION SEMTECH TELEDYNE TECHNOLOGIES PMC SIERRA HONEYWELL INTERNATIONAL MITSUBISHI HEWLETT PACKARD TOSHIBA X FAB SWINDON SILICON SYSTEMS MURATA TOWER SEMICONDUCTOR SIGMA DESIGNS CANON ADVANTEST RF MICRO DEVICES MICROSEMI MICRON TECHNOLOGY ENTROPIC COMMUNICATIONS INTERSIL PEREGRINE SEMICONDUCTOR LUXTERA CONEXANT SYSTEMS OMNIVISION TECHNOLOGIES GALAXYCORE INTEGRATED DEVICE TECHNOLOGY E2V ALTERA NVIDIA CLARIPHY COMMUNICATIONS COHERENT SPANSION ST JUDE MEDICAL WOLFSON MICROELECTRONICS TEXAS INSTRUMENTS INFINEON CSMC TECHNOLOGIES FORZA SILICON SYMMID BIOTRONIK PANASONIC DE SHAW GROUP INSIDE TECHNOLOGIES MIET VOLTERRA SWATCH TERADYNE SPREE SILICON SYSTEM TOUMAZ TECHNOLOGY ALTAIR HUAWEI TECHNOLOGIES CORTINA SYSTEMS INVISAGE RF INTEGRATION ZMD CHRONTEL HILIGHT SEMICONDUCTOR AMBIQ MICRO INPHI CIMPACA RAYSAT CEITEC GIANTEC SEMICONDUCTOR SPREADTRUM COMMUNICATIONS VANGUARD INTL SEMICONDUCTOR LIME MICROSYSTEMS AVAGO TECHNOLOGIES RUSSIAN SPACE SYSTEMS MIKRON ZAO GENNUM ENPHASE ENERGY GOOGLE PARROT AMAZING MICROELECTRONIC SMIC SHANGHAI HUALI MICROELECTRONICS S SILTERRA 100+ CUSTOMERS GLOBALLY IPVS, PVSCV, PVS PERC, PVS SIGNOFF 13 TOP SEMICONDUCTOR COMPANIES OF THE Transitioning to In-Design and Signoff PVS © 2013 Cadence Design Systems, Inc. All rights reserved.

7© 2013 Cadence Design Systems, Inc. All rights reserved. Faster Path to Sign-Off with In-Design PVS 80% time spent debugging 20% on runtime Virtuoso Custom IC Platform Virtuoso Custom IC Platform PVS Signoff Faster Turnaround Time Efficient Debugging Efficient Debugging Tight Integration Encounter Digital Platform Encounter Digital Platform In-Design PVS Higher Productivity Higher Productivity In-Design PVS Verification Time to Tapeout Source: Cadence

8© 2013 Cadence Design Systems, Inc. All rights reserved. Improved Productivity with PVS Signoff BEST - Virtuoso IPVS Dynamic In-Design Verification, checks as you edit Design Platform Layout Seat Standalone PVS signoff Standalone PVS signoff Std Interfaces Enhances Productivity of Layout Teams PVS Verify Design PVS Verify Design In Memory Dynamic IPVS Dynamic IPVS GDSII BETTER - PVS interactive (batch) signoff executing off Virtuoso ® in-memory data INEFFICIENT - Traditional (batch) signoff forces long loops Live Demo in Lobby

9© 2013 Cadence Design Systems, Inc. All rights reserved. Coming Up - Customer experience of adopting PVS