Copyright © 2002 Delmar Thomson Learning Chapter 15 Timer and Counter Instructions
Copyright © 2002 Delmar Thomson Learning Objectives Describe the function of an on-delay timer. Describe the function of an off-delay timer. Describe in what instances one would use a retentive timer. Describe the function of an up counter. Describe the function of a down counter.
Copyright © 2002 Delmar Thomson Learning Objectives (cont’d.) Describe in what instances one would use an up counter versus a down counter. Define preset, accumulative value, and the timer or counter address. Explain how the various timers and counters are reset.
Copyright © 2002 Delmar Thomson Learning T4, Timer File The timer file stores only timer elements. An element is a word or group of words that work together as a unit. A timer is made of of three pieces or words: Preset value Accumulated value Status bits
Copyright © 2002 Delmar Thomson Learning T4, Timer File (cont’d.) The preset value and accumulated value are 16-bit signed integers. Status bits are single bits that make up one 16-bit word. These three words work together as a unit.
Copyright © 2002 Delmar Thomson Learning One Timer Element Is Made of Three 16-Bit Words
Copyright © 2002 Delmar Thomson Learning Timer Addressing Sample timer element addressT4:2 T4 = timer file 4 :2 = timer element #2 (0-255 timer elements per file)
Copyright © 2002 Delmar Thomson Learning Sub-Element A sub-element is part of an element addressable as a unit. The preset value and accumulated value are sub-elements of a timer: T4:0.PRE T4:0.ACC
Copyright © 2002 Delmar Thomson Learning Timer Status Bits Timers have three status bits. Done bit (DN) is true when the accumulated value and preset are equal. Timer timing bit (TT) is true when the timer is timing. Enable bit (EN) is true when the timer instruction is enabled or true.
Copyright © 2002 Delmar Thomson Learning Timer Bit Addressing Status bit addresses for timer file 4, timer element 2 (T4:2) are listed below: T4:2/DN is the address for the done bit. T4:2/EN is the address for the enable bit. T4:2/TT is the address for the timer timing bit.
Copyright © 2002 Delmar Thomson Learning Timer File T4
Copyright © 2002 Delmar Thomson Learning C5, Counter File The counter file stores only counter elements. An element is a word or group of words that work together as a unit. A counter is made of of three pieces or words: Preset value Accumulated value Status bits
Copyright © 2002 Delmar Thomson Learning C5, Counter File (cont’d.) The preset value and accumulated value are 16-bit signed integers. Status bits are single bits that make up one 16-bit word. These three words work together as a unit.
Copyright © 2002 Delmar Thomson Learning One Counter Element Is Made of Three 16-Bit Words
Copyright © 2002 Delmar Thomson Learning Counter Addressing Sample counter element address C5:2 C5 = timer file 5 :2 = counter element #2 (0-255 timer elements per file)
Copyright © 2002 Delmar Thomson Learning Sub-Element A sub-element is part of an element addressable as a unit. The preset value and accumulated value are sub-elements of a counter: C5:0.PRE C5:0.ACC
Copyright © 2002 Delmar Thomson Learning Counter Status Bits Counters have five status bits. Done bit (DN) is true when the accumulated value and preset are equal. Count up enable bit (CU) is true when the up counter is true or enabled. Count down enable bit (CD) is true when the count down counter is enabled or true.
Copyright © 2002 Delmar Thomson Learning Counter Status Bits (cont’d.) The overflow bit (OV) is true when the up counter has overflowed above The underflow bit (UN) is true when the down counter has underflowed below The update accumulator bit (UA) is a high- speed counter status bit for fixed SLC 500 PLCs.
Copyright © 2002 Delmar Thomson Learning Counter Status Bit Addressing Status bit addresses for counter file 5, counter element 0 (C5:0) are listed below: C5:0/DN is the address for the done bit. C5:0/CU is the address for the count up enable bit.
Copyright © 2002 Delmar Thomson Learning Counter Status Bit Addressing (cont’d.) C5:0/CD is the address for the count down enable bit. C5:0/OV is the address for the count up overflow bit. C5:0/UN is the address for the count down underflow bit.
Copyright © 2002 Delmar Thomson Learning Counter File C5
Copyright © 2002 Delmar Thomson Learning SLC 500 On-Delay Timer
Copyright © 2002 Delmar Thomson Learning SLC 500 Timer Instructions
Copyright © 2002 Delmar Thomson Learning SLC 500 On-Delay Timer and Associated Status Bits
Copyright © 2002 Delmar Thomson Learning SLC 500 Off-Delay Timer
Copyright © 2002 Delmar Thomson Learning SLC 500 Retentive Timer
Copyright © 2002 Delmar Thomson Learning Retentive Timer and Its Reset Instruction
Copyright © 2002 Delmar Thomson Learning SLC 500 Counters
Copyright © 2002 Delmar Thomson Learning SLC 500 Count Up Counter
Copyright © 2002 Delmar Thomson Learning SLC 500 Count Down Counter
Copyright © 2002 Delmar Thomson Learning SLC 500 Count Down Counter Instruction
Copyright © 2002 Delmar Thomson Learning Reset Instruction to Reset Counter C20:7
Copyright © 2002 Delmar Thomson Learning Using the Clear Instruction to Clear C5:0.ACC and C5:1.Acc