EE5342 – Semiconductor Device Modeling and Characterization Lecture 30 May 05, 2010 Professor Ronald L. Carter

dt for VBIC-R1.5 model Model: VBIC-R1.5. “selft” flag set to 1. No optimization done. No external circuit connected. Rth=5.8E+0 Cth=96E-12 2L30 05/05/10

VBIC-R1.5 Y11 plot (standard data) 3L30 05/05/10

VBIC-R1.5 Y11 plot (standard data) 4L30 05/05/10

VBIC-R1.2 Y11 plot (optimized data) 5 For optimized data refer slide “Model Parameters”. Circuit used is shown in “Circuit for Y parameters (optimized data)” slide. fc Τ fc1= 2E E-05 fc2= 9.25E E-06 fc3= 3.2E E-08 Fc4=2E E-05 Fc5=1E E-06 Fc6=4E E-08 fc7= 2E E-05 fc8= 1E E-06 fc9=4E E-08 L30 05/05/10

Spreadsheet for Calculating the Rth and Cth Calculations mentioned in the previous slides have been implemented in an Excel spreadsheet. The Cauer to Foster network transformation is done.  The spreadsheet takes the dimensions of different layers of the devices and gives corresponding Cauer and Foster network values. This enables the calculation of time constants which can be converted into a single pole. The characteristic times for the Foster network appear on a impulse response plot. L30 05/05/106 Fig. 7. Electrical equivalent Cauer network of the HBTFig. 8. Electrical equivalent Foster network of the HBT

IC-CAP Simulations L30 05/05/107

8 Effect of Rth on current feedback op-amp settling time -+-+ v IN = 1 V P-P,  = 200  -sec 500  v OUT 100 

L30 05/05/109 Current Feedback Op Amp Data (LMH6704) Switching Offset

L30 05/05/1010 LMH6550 impulse thermal characteristics LeCroy sampling oscilloscope (1M  input mode) Maximum averaging (10000) Input nominally +/- 1V with 50 micro-sec period and 50% duty cycle. Fractional Gain Error = FGE

L30 05/05/1011 vIN Rising Response vOUT vIN FGE

L30 05/05/1012 vIN Falling Response vOUT vIN FGE

Current Feedback Op-Amp (CFOA) with Simple Current Mirror (CM) Bias sup L30 05/05/1013

Large-signal Output Voltage Transient Analysis for CFOA with Simple CM Biasing L30 05/05/1014

Hypothesis: The Thermal Tail is a Linear Superposition of the Contribution from each Individual Circuit Stick The contribution of individual transistor to the total thermal tail. Used six stick classifications according to transistor type and functionality. i.e. Q 10  stk3-pnp-bf and Q 11  stk4-npn-cm Enabled the self-heating effect in the stick of interest and disabled the self-heating effect of the remaining transistors. Simulated the contribution of each individual stick. The total thermal tail simulated is essentially the sum of the individual thermal tail contributions of each circuit stick. L30 05/05/1015

The Hypothesis Supported Area x1 Area x8 Thermal Tail (uV/V)High-to-LowLow-to-HighHigh-to-LowLow-to-High stk2-npn-bf (Q 5 ) stk2-pnp-bf (Q 6 ) stk2-npn-cm (Q 2 ) stk2-pnp-cm (Q 4 ) stk3-npn-bf (Q 7 ) stk3-pnp-bf (Q 8 ) stk4-npn-cm (Q 12 ) stk4-pnp-cm (Q 10 ) stk5-npn-bf(Q 13 ) stk5-pnp-bf(Q 14 )-441 stk5-npn-cm(Q 18 ) stk5-pnp-cm(Q 17 )-5200 stk6-npn-bf(Q 15 )0100 stk6-pnp-bf(Q 16 )000 added total simulated total L30 05/05/1016

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L30 05/05/1018 Heterojunction Electrostatics EoEo E C,p E V,p E F,p E F,n E C,n E V,n ECEC EVEV qpqp qnqn -x n xpxp 0

L30 05/05/1019 Poisson’s Equation ExEx x xpxp -x n

L30 05/05/1020 Heterojunction electronics

L30 05/05/1021 Heterojunction electronics (cont)

L30 05/05/1022 Heterojunction electronics (cont)

L30 05/05/1023 Heterojunction depletion widths

L30 05/05/1024 References Fujiang Lin, et al, “Extraction Of VBIC Model for SiGe HBTs Made Easy by Going Through Gummel-Poon Model”, from n.pdf Avanti Star-spice User Manual, 04, Affirma Spectre Circuit Simulator Device Model Equations Zweidinger, D.T.; Fox, R.M., et al, “ Equivalent circuit modeling of static substrate thermal coupling using VCVS representation ”, Solid-State Circuits, IEEE Journal of, Volume: 2 Issue: 9, Sept. 2002, Page(s):

Thermal Analogy References [1] I.Z. Mitrovic, O. Buiu, S. Hall, D.M. Bagnall and P. Ashburn “Review of SiGe HBTs on SOI”, Solid State Electronics, Sept. 2005, Vol. 49, pp [2] Masana, F. N., “A New Approach to the Dynamic Thermal Modeling of Semiconductor Packages”, Microelectron. Reliab., 41, 2001, pp. 901–912. [3] Richard C. Joy and E. S. Schlig, “Thermal Properties of Very Fast Transistors”, IEEE Trans. ED, ED-1 7. No. 8, August 1970, pp [4] Kevin Bastin, “Analysis and Modeling of self heating in SiGe HBTs”, Aug. 2009, Masters Thesis, UTA. [5] Rinaldi, N., “On the Modeling of the Transient Thermal Behavior of Semiconductor Devices”, IEEE Trans-ED, Volume: 48, Issue: 12, Dec. 2001; Pages:2796 – L30 05/05/1025

Simulation … References [1] E. Castro, S. Coco, A. Laudani, L. LO Nigro and G. Pollicino, “A New Tool For Bipolar Transistor Characterization Based on HICUM”, Communications to SIMAI Congress, ISSN , Vol. 2, [2] K. Bastin, “Analysis And Modeling of Self Heating in Silicon Germanium Heterojunction Bipolar Transistors”, Thesis report, The University of Texas at Arlington, August L30 05/05/10

AICR Team at University of Texas Arlington - Electrical Engineering Current Ronald L. Carter, Professor W. Alan Davis, Associate Professor Howard T. Russell, Senior Lecturer Ardasheir Rahman 1 Ratan Pulugurta 1 Xuesong Xie 1 Arun Thomas-Karingada 2 Sharath Patil 2 Valay Shah 2 Earlier Contributors Kevin Bastin, MS Abhijit Chaugule, MS Daewoo Kim, PhD Anurag Lakhlani, MS Zheng Li, PhD Kamal Sinha, PhD 1 PhD Student 2 MS Student L30 05/05/1027