External Memory Interface (EMIF) Chapter 13 C6000 Integration Workshop Copyright © 2005 Texas Instruments. All rights reserved. Technical Training Organization T TO

Outline  Memory Maps  Device  DSK  Memory Types  Overview  SDRAM Specifics  ASYNC Specifics  Programming the EMIF  CSL  Assembly  Lab Exercise  Additional Memory Topics  Performance  Fanout / System  Shared Memory (HOLD, HOLDA)  EMIF Variations  SBSRAM Specifics  SDRAM Optimization  Flash "Programming" Technical Training Organization T TO

Outline  Memory Maps  Memory Types  Programming the EMIF  Additional Memory Topics Technical Training Organization T TO

Outline  Memory Maps  Device  DSK  Memory Types  Programming the EMIF  Lab Exercise  Additional Memory Topics Technical Training Organization T TO

Memory Map Review 8000_ MB CE3 9000_0000 B000_ MB CE2 128MB CE1 128MBCE0 A000_ MB 8000_0000 CE0 A000_0000 CE2 C6000 CPU L2 SRAM EMIF 64KBL2 SRAM B000_0000 CE3 9000_0000 CE1 128 MB 0000_0000 A Memory Map is a table representation of memory… Technical Training Organization T TO

FFFF_FFFF 0000_ KB Internal Program / Data Peripheral Regs 0180_ MB External 8000_ _0000 A000_0000 B000_ MB External TMS320C6713 Available via Daughter Card Connector ‘C6713 DSK 16MB SDRAM 256K byte FLASH CPLD C6713 DSK Memory Map CPLD:   LED’s   DIP Switches   DSK status   DSK rev#   Daughter Card 9008_0000

C6416 DSK Memory Map CPLD:   LED’s   DIP Switches   DSK status   DSK rev#   Daughter Card 0000_0000 Internal RAM: 1MB 0010_0000 Internal Peripherals or reserved 6000_0000 EMIFB CE0 : 64MB CPLD 6400_0000 EMIFB CE1 : 64MB Flash: 512KB 6800_0000 EMIFB CE2 : 64MB 6C00_0000 EMIFB CE3 : 64MB 8000_0000 EMIFA CE0 : 256MB SDRAM: 16MB 9000_0000 EMIFA CE1 : 256MB A000_0000 EMIFA CE2 : 256MB Daughter Card B000_0000 EMIFA CE3 : 256MB TMS320C6416C6416 DSK Technical Training Organization T TO

Memory Maps FFFF_FFFF 0000_ KB Internal Program / Data Peripheral Regs 0180_ MB External 8000_ _0000 A000_0000 B000_ MB External TMS320C h Available via Daughter Card Connector ‘C6711 DSK 16MB SDRAM 128K byte FLASH 4 byte I/O Port   LED’s   Switches   DSK status   DSK rev# Click Here for description of Address Pins Technical Training Organization T TO

CE Pins Select Memory Space FFFF_FFFF 0000_0000 C6000 CPU L2 Internal Memory EMIF 64KB Internal (Program or Data) On-chip Periph 128MB External CE0 CE1 CE2 CE3 Technical Training Organization T TO

‘C6x Addressing CPU DMA or EDMA EMIF A2:A21   With only 20 address pins, only SDRAM can access full 128M Bytes per CE space   Not all CPU/DMA address lines are used in C6x01 example above EA2-21 A0:A1 BE0 BE1 BE2 BE3 A24:A25 CE0 CE1 CE2 CE3 Technical Training Organization T TO

Outline Memory Maps   Memory Types   Overview   Selecting a Memory Type   SDRAM Specifics   ASYNC Specifics   Programming the EMIF   Lab Exercise   Additional Memory Topics Technical Training Organization T TO

SDRAM - Synchronous (clocked) DRAM   SDRAM provides lowest cost / bitcheap   Operates up to 100 MHzfast   Built-in SDRAM controller makes interfacing simpleeasy   Only SDRAM can reach full address spacebig Memory Types Overview 16M Byte SDRAM CPU EDMA EMIF ASYNC - Traditional (unclocked) memories   Wide array of memories (Flash, SRAM, Regs, FPGA/ASIC)   Can use buffer/drivers, address decoding, etc.flexible   Allows multiprocessor accessshare Flash (ASYNC) I/O Port (ASYNC) Note: SBSRAM is covered later in the chapter - it's not implemented on the DSK

Selecting Memory Type Global Control SDRAM Refresh Prd SDRAM Control 180_001C 180_ _ _0020 MTYPE 7 4 CEx Control Register RW, b = 8-bit-wide Async 0001b = 16-bit-wide Async 0010b = 32-bit-wide Async 0011b = 32-bit-wide SDRAM 0100b = 32-bit-wide SBSRAM 1000b = 8-bit-wide SDRAM 1001b = 16-bit-wide SDRAM 1010b = 8-bit-wide SBSRAM 1011b = 16-bit-wide SBSRAM SDRAM Extension CE1 Control CE3 Control CE0 Control CE2 Control 180_ _ _ _0010 Technical Training Organization T TO

EMIF Registers CE1 Control CE3 Control CE0 Control CE2 Control Global Control SDRAM Refresh Prd SDRAM Control 180_ _ _ _ _001C 180_ _0000 SDRAM Extension 180_ _0000 L2 SRAM Peripheral Regs 0180_0000 CE2 CE3 8000_ _0000 A000_0000 B000_0000 CE0 CE1 TMS320C6711 Technical Training Organization T TO

Outline Memory Maps   Memory Types Overview Selecting a Memory Type   Using SDRAM   Using ASYNC   Programming the EMIF   Additional Memory Topics Technical Training Organization T TO

Using SDRAM Select SDRAM and verify it meets system performance timing   Due to high MHz bus frequencies, we provide some practical suggestions on the next 2 slides Setup SDRAM control registers Calculate SDRAM refresh timing (period) Technical Training Organization T TO

DM642 SDRAM Recommendations   Due to datasheet requirements, the following is recommended:   1 bank (max of 2 chips) of SDRAM connected to EMIF   Up to 1 bank of buffers connected to EMIF for async memories   Trace lengths between 1 and 3 inches   183MHz SDRAM for 133MHz EMIF operation   143MHz SDRAM for 100MHz EMIF operation   Therefore:   To run the EMIF at 133MHz and meet the above requirements, the largest memory size available today is 16M Bytes using two 2Mx32 SDRAMs.   Alternatively:   The largest memory size achievable using x32 devices is 32MBytes using 4Mx32 SDRAMs. However, these devices are only available at 166Mhz.   Another option is to use x16 devices, but you have to use four of these since the EMIF is 64 bits wide. Also, the fastest speed grade is 167MHz. * These guidelines are for DM642 in June Other C6000 devices require similar consideration. Technical Training Organization T TO

SDRAM Design Considerations   Use Daisy chaining or minimum stub length routing on EMIF signals   Keep trace lengths as close as possible to the same length   ‘Swizzle’ signals such that they are flow through to avoid signal criss- crossing as much as possible. For example, on resistor packs or SDRAM data pins on a ‘byte’ boundary   Serial termination resistors should be inserted into all EMIF output signal lines to maintain signal integrity   Use controlled impedance of ohms on layout/pwb fabrication   Ground layer is a must, and can be duplicated to help with controlled impedance any time there is an odd number of layers   Perform timing analysis to verify A/C timings are met using I/O Buffer Information Specification (IBIS)   In fact, using IBIS modeling you may find you can improve upon the suggestions provided on the previous slide   Refer to application note: Using IBIS Models for Timing Analysis Technical Training Organization T TO

What is IBIS?  General IBIS Information:  Technical Training Organization T TO

What are these models based on? Technical Training Organization T TO

Model Characteristics Technical Training Organization T TO

Using SDRAM Select SDRAM and verify it meets system performance timing Setup SDRAM control registers   Read values off SDRAM data sheet to set control register values Calculate SDRAM refresh timing (period) Technical Training Organization T TO

SDRAM Control Register   Calculate the number of cycles for each of the three timing parameters using the SDRAM datasheet. The following formula may help: TR__ = (t RCD / t ECLKOUT ) – 1   There’s only one SDRAM Control Register, therefore all SDRAM spaces must have the same configuration TRP TRCD TRC reserved rsv Technical Training Organization T TO

SDRAM Control Register   TRCD = 30ns / 10ns - 1 = 2   TRP = 30ns / 10ns - 1 = 2   TRC = 90ns / 10ns - 1 = 8 From SDRAM Datasheet EMIF Clockspeed TRP TRCD TRC reserved rsv Technical Training Organization T TO

SDRAM Control Register   Oh, here’s a couple other small details: SDRAM Column Size (SDCSZ) 00 = 9 pins (512) 01 = 8 pins (256) 10 = 10 pins (1024) 11 = reserved SDRAM Column Size (SDCSZ) 00 = 9 pins (512) 01 = 8 pins (256) 10 = 10 pins (1024) 11 = reserved TRP TRCD TRC reserved SDCSZ rsv

SDRAM Control Register   Oh, here’s a couple other small details: SDRAM Column Size (SDCSZ) 00 = 9 pins (512) 01 = 8 pins (256) 10 = 10 pins (1024) 11 = reserved SDRAM Column Size (SDCSZ) 00 = 9 pins (512) 01 = 8 pins (256) 10 = 10 pins (1024) 11 = reserved SDRAM Row Size (SDRSZ) 00 = 11 pins (2048) 01 = 12 pins (4096) 10 = 13 pins (8192) 11 = reserved SDRAM Row Size (SDRSZ) 00 = 11 pins (2048) 01 = 12 pins (4096) 10 = 13 pins (8192) 11 = reserved TRP TRCD TRC SDRSZ reserved SDCSZ rsv

SDRAM Control Register   Oh, here’s a couple other small details: TRP TRCD TRC SDRSZ reserved SDCSZ SDBSZ SDRAM Column Size (SDCSZ) 00 = 9 pins (512) 01 = 8 pins (256) 10 = 10 pins (1024) 11 = reserved SDRAM Column Size (SDCSZ) 00 = 9 pins (512) 01 = 8 pins (256) 10 = 10 pins (1024) 11 = reserved SDRAM Row Size (SDRSZ) 00 = 11 pins (2048) 01 = 12 pins (4096) 10 = 13 pins (8192) 11 = reserved SDRAM Row Size (SDRSZ) 00 = 11 pins (2048) 01 = 12 pins (4096) 10 = 13 pins (8192) 11 = reserved SDRAM Bank Size (SDBSZ) 0 = 1 pin (2) 1 = 2 pins (4) SDRAM Bank Size (SDBSZ) 0 = 1 pin (2) 1 = 2 pins (4) rsv

SDRAM Control Register   Oh, here’s a couple other small details: TRP TRCD TRC SDRSZInit reserved SDCSZ SDBSZ SDRAM Column Size (SDCSZ) 00 = 9 pins (512) 01 = 8 pins (256) 10 = 10 pins (1024) 11 = reserved SDRAM Column Size (SDCSZ) 00 = 9 pins (512) 01 = 8 pins (256) 10 = 10 pins (1024) 11 = reserved SDRAM Row Size (SDRSZ) 00 = 11 pins (2048) 01 = 12 pins (4096) 10 = 13 pins (8192) 11 = reserved SDRAM Row Size (SDRSZ) 00 = 11 pins (2048) 01 = 12 pins (4096) 10 = 13 pins (8192) 11 = reserved SDRAM Bank Size (SDBSZ) 0 = 1 pin (2) 1 = 2 pins (4) SDRAM Bank Size (SDBSZ) 0 = 1 pin (2) 1 = 2 pins (4) Initialization (INIT) 0 = No effect 1 = Initialize Initialization (INIT) 0 = No effect 1 = Initialize rsv

SDRAM Control Register   Oh, here’s a couple other small details: TRP TRCD TRC SDRSZINIT reserved RFENSDCSZ SDBSZ ‘C6x does Refresh (REFEN) 0 = No 1 = Yes ‘C6x does Refresh (REFEN) 0 = No 1 = Yes rsv SDRAM Column Size (SDCSZ) 00 = 9 pins (512) 01 = 8 pins (256) 10 = 10 pins (1024) 11 = reserved SDRAM Column Size (SDCSZ) 00 = 9 pins (512) 01 = 8 pins (256) 10 = 10 pins (1024) 11 = reserved SDRAM Row Size (SDRSZ) 00 = 11 pins (2048) 01 = 12 pins (4096) 10 = 13 pins (8192) 11 = reserved SDRAM Row Size (SDRSZ) 00 = 11 pins (2048) 01 = 12 pins (4096) 10 = 13 pins (8192) 11 = reserved SDRAM Bank Size (SDBSZ) 0 = 1 pin (2) 1 = 2 pins (4) SDRAM Bank Size (SDBSZ) 0 = 1 pin (2) 1 = 2 pins (4) Initialization (INIT) 0 = No effect 1 = Initialize Initialization (INIT) 0 = No effect 1 = Initialize

Using SDRAM Select SDRAM and verify it meets system performance timing Setup SDRAM control registers Calculate SDRAM refresh timing   And program SDRAM refresh timing register Technical Training Organization T TO

SDRAM Refresh Timing Register = 1562 (0x61A) From the SDRAM data sheet: Refresh Rate= “4K Auto Refresh each 64ms” = 64 ms / 4096 Period Counter reserved R, +0RW, +00R, RW, XRFR Assuming 100MHz EMIF Clockspeed = (64ms/4096) / 10ns Period = t Refresh Rate / t ECLK Technical Training Organization T TO

Outline - Memory Types Overview Selecting a Memory Type Using SDRAM   Using ASYNC   Generic Read Timing   Async Example - Flash   Flash Read Timing   Flash Write Procedure Technical Training Organization T TO

Memory A D ADAD ADAD ADAD Access 1 Access 2 Access 3 Asynchronous Memory - What is it?   Traditional Memory Interface   Doesn’t require clock   Non Pipelined Accesses   Ex: SRAM, EPROM, Regs, Ext. Periph   External buffers can be used for:   Shared memory   Increased fanout   Isolation Technical Training Organization T TO

Async Read Timing ECLKOUT EA, CE, BE AOE

Async Read Timing SetupStrobeHold ECLKOUT AOE ARE ED EA, CE, BE Technical Training Organization T TO

Setup = 1Strobe = 2Hold = 1 Async Read Timing ECLKOUT AOE ARE C6x11 range: Read Hold MTYPE Read Strobe Read Setup CEx Register ED EA, CE, BE Technical Training Organization T TO

What is Flash Memory  DSK has 128K Flash*  Provides re-programmable non- volatile memory  Used to store initialization values  Stores constants used at run time  Host programming tools provided  Target APIs for programming included in BSL * Async Flash example is discussed for C6711 DSK. Technical Training Organization T TO

Flash Read Timing h Available via Daughter Card Connector C6711 DSK 16MB SDRAM 128KB FLASH 4 byte I/O Port   LED’s   Switches   DSK status   DSK rev# h   DSK has 128K Flash   Provides re-programmable, non-volatile memory   Pre-program with code, init values and boot-strap program   Stores non-volatile, run-time data Looking more closely at the timing … Technical Training Organization T TO

Flash Read Timing Setup= ______ Strobe= ______ Hold= ______ Let's figure out the timing for the DSK's async Flash memory … 150ns 100ns 150ns 0ns 50ns Use EMIF’s ARE pin Technical Training Organization T TO

Flash Read Timing 150ns 100ns 150ns 0ns 50ns Setup= ______ Strobe= ______ Hold= ______ Note:Memory timing is highly dependent upon board-related design factors. While this example approximates the DSK timing, your board requirements may differ Use EMIF’s ARE pin

Flash Memory 'C6x11 EMIF AddressEA[18:2] DataED[7:0] Write Enable AWE Output Enable ARE Chip Enable CE [1] A[16:0] I/O[7:0] WE OE CE FLASH Technical Training Organization T TO

Writing to DSK's Flash   Flash is a non-volatile memory, i.e. it can't normally be written to   To change it's content, you must "unlock" it with a special procedure:   PC based tools available for Flash programming   BSL functions allow runtime writing to Flash Write 0xAA to 0x Write 0x55 to 0x2AAA Write 0xA0 to 0x Write new data to 128 byte sector (data must be written in 128 byte chunks)   Flash requires 20ms to complete internal write cycle. Data I/O7 can be polled to determine when write cycle is complete. Technical Training Organization T TO

Timing & Table Available via Daughter Card Connector C6711 DSK 16MB SDRAM 128KB FLASH 4 byte I/O Port CE1 Technical Training Organization T TO

Using Async Generic Read Timing Flash Read Timing Flash Write Procedure   Optional   Maximum Async Performance   Generic Async Write Timing   Bus Turnaround Time Technical Training Organization T TO

Async Read - Maximum Speed Setup = 1Strobe=1Hold = 0 ECLKOUT EA, CE, BE AOE ARE ED Technical Training Organization T TO

Async Write Timing SetupStrobeHold ECLKOUT AWE EA, CE, BE ED Write HoldWrite Strobe Write Setup Technical Training Organization T TO

Minimum Turn-Around Time   First R/W in a series requires an extra “setup” cycle Read Bus Turn-AroundWrite CE EA, BE AOE ARE AWE ED   CE on last access is held active for a minimum of 7 cycles   Bus turn-around time (R  W or W  R) is approx 9 cycles (please refer to data sheet for specifics for each individual processor) Technical Training Organization T TO

Async Memory - Summary Cycles Setup=1 * - 15 Read Hold = Strobe=1 * - 63 Write Hold = Cycles Setup=1 * - 15 Read Hold = Strobe=1 * - 63 Write Hold = * 0  1 and 1  1 Read Setup Write Hold Write Strobe Write Setup RW, +1111RW, RW, +11RW, Read Hold rsv MTYPE TA Read Strobe RW, RW, +0010RW, b = 8-bit-wide Async 0001b = 16-bit-wide Async 0010b = 32-bit-wide Async 0011b = 32-bit-wide SDRAM 0100b = 32-bit-wide SBSRAM 1000b = 8-bit-wide SDRAM 1001b = 16-bit-wide SDRAM 1010b = 8-bit-wide SBSRAM 1011b = 16-bit-wide SBSRAM Technical Training Organization T TO

Outline  Memory Maps  Memory Types  Programming the EMIF  C language via CSL  Assembly  GEL  Additional Memory Topics Technical Training Organization T TO

Program EMIF with CSL far const EMIFA_Config C6416DskEmifConfigA = { EMIF_GBLCTL_RMK( // 0x EMIF_GBLCTL_EK2RATE_FULLCLK, // bits = 00 EMIF_GBLCTL_EK2HZ_CLK, // bit 17 = 0 EMIF_GBLCTL_EK2EN_ENABLE, // bit 16 = 1 EMIF_GBLCTL_BRMODE_MRSTATUS, // bit 13 = 1 EMIF_GBLCTL_BUSREQ_LOW, // bit 11 = 0... EMIF_GBLCTL_CLK6EN_DISABLE, // bit 3 = 0 ); 0x , /* cectl0 **/... 0x /* cesec3 */ }; void emifInit(){ EMIFA_config(&C6416DskEmifConfigA); }   Program EMIF similar to other peripherals.   Since EMIF is not a multi-channel periperhal, no _open function is required. Technical Training Organization T TO

Program EMIF with Assembly (1) EMIF.equ0x GBLCTL.equ0x________ CE0CTL.equ0x________ CE1CTL.equ0x________ CE2CTL.equ0x________ CE3CTL.equ0x________ SDCTL.equ0x________ SDTIM.equ0x________ SDOPT.equ0x________ cEMIF:mvklEMIF, A0 mvkhEMIF, A0 mvklGBLCTL, A1 mvkhGBLCTL, A1 stwA1,*+A0[0] mvklCE0CTL, A1 mvkhCE0CTL, A1 stwA1,*+A0[2] … mvkhSDOPT, A1 stwA1,*+A0[8] Global Control SDRAM Ref Prd SDRAM Control 180_001C 180_ _ _0020 SDRAM Extension CE1 Control CE3 Control CE0 Control CE2 Control 180_ _ _ _0010   Add the desired register values to the blank spaces and code will program EMIF   Assembly code will work for all devices, if you … Better yet, … Technical Training Organization T TO

Program EMIF with Assembly (2) /* Include Header File #include “csl_emif.h” /* Config Structures */ far const EMIF_Config myEM 0x , /* Global Control Reg. (GBLCTL) */ 0x , /* CE0 Space Control Reg. (CE0CTL)*/ 0xFFFF3F23, /* CE1 Space Control Reg. (CE1CTL)*/ 0x , /* CE2 Space Control Reg. (CE2CTL)*/ 0xFFFF3F23, /* CE3 Space Control Reg. (CE3CTL)*/ 0x0388F000, /* SDRAM Control Reg.(SDCTL) */ 0x /* SDRAM Timing Reg.(SDTIM) */ 0x00F02AE0 /* SDR };.global _myEMIF EMIF.equ0x cEMIF: mvkl EMIF, A0 mvkh EMIF, A0 mvkl _myEMIF, A1 mvkh _myEMIF, A1 ldw *A1, A2 stw A2, *A0 ldw *++A1[1], A2 stw A2, *+A0[2]... ldw *++A1[1], A2 stw A2, *+A0[8]   Create EMIF_Config structure and use assembly to write configuration values to peripheral   Note: must use “far const” declaration for this method to work Technical Training Organization T TO

init_emif(){ // First we define the EMIF addresses #define EMIF_GCTL 0x #define EMIF_CE1 0x #define EMIF_CE0 0x #define EMIF_CE2 0x #define EMIF_CE3 0x #define EMIF_SDRAMCTL 0x #define EMIF_SDRAMTIMING 0x C #define EMIF_SDRAMEXT 0x // Now we set the values *(int *)EMIF_GCTL = 0x ; // EMIF global *(int *)EMIF_CE0 = 0x ; // CE0-SDRAM *(int *)EMIF_CE2 = 0xFFFFFF23; // CE2-32bit async on daughtercard *(int *)EMIF_CE3 = 0xFFFFFF23; // CE3-32bit async on daughtercard *(int *)EMIF_SDRAMCTL = 0x ; // SDRAM control register(100 MHz) *(int *)EMIF_SDRAMTIMING = 0x A;// SDRAM Timing register *(int *)EMIF_SDRAMEXT = 0x ; // SDRAM Extension register } init_emif(){ // First we define the EMIF addresses #define EMIF_GCTL 0x #define EMIF_CE1 0x #define EMIF_CE0 0x #define EMIF_CE2 0x #define EMIF_CE3 0x #define EMIF_SDRAMCTL 0x #define EMIF_SDRAMTIMING 0x C #define EMIF_SDRAMEXT 0x // Now we set the values *(int *)EMIF_GCTL = 0x ; // EMIF global *(int *)EMIF_CE0 = 0x ; // CE0-SDRAM *(int *)EMIF_CE2 = 0xFFFFFF23; // CE2-32bit async on daughtercard *(int *)EMIF_CE3 = 0xFFFFFF23; // CE3-32bit async on daughtercard *(int *)EMIF_SDRAMCTL = 0x ; // SDRAM control register(100 MHz) *(int *)EMIF_SDRAMTIMING = 0x A;// SDRAM Timing register *(int *)EMIF_SDRAMEXT = 0x ; // SDRAM Extension register } Program EMIF with GEL When does this GEL script get executed?

/* * The StartUp() function is called every time you start Code Composer. * You can customize this function to perform desired initialization. * This function may be commented out if no initialization is needed. */ StartUp() { setup_memory_map(); GEL_Reset(); init_emif(); } /* * The StartUp() function is called every time you start Code Composer. * You can customize this function to perform desired initialization. * This function may be commented out if no initialization is needed. */ StartUp() { setup_memory_map(); GEL_Reset(); init_emif(); } Open DSK6211_6711.gel GEL Startup Technical Training Organization T TO

Outline  Memory Maps  Memory Types  Programming the EMIF  Additional Memory Topics Technical Training Organization T TO

Lab 13  Main Lab  Write EMIF Init Function using CSL  Optional Lab's  Write EMIF init using assembly  Remove EMIF initialization code from GEL file  Read/Write Flash using BSL functions Technical Training Organization T TO

Additional Memory Topics   Performance Considerations   Fanout / System   Shared Memory ( HOLD, HOLDA )   Overview of SBSRAM   SDRAM Optimization   C6000 Family EMIF Comparison Technical Training Organization T TO

1 cycle ~ 8 cycles 1 cycle ~ 1 cycle 1 cycle 14 cycles Performance Assuming no wait-states, how many cycles does it take for... Program Fetch: DMA Read: LD Instruction: InternalExternal Technical Training Organization T TO

DMC 1 2 mem ‘C6201 PC 3 4 regs CPU Load from Internal Memory   Even though an internal memory access requires a four cycle access time, as with most modern RISC processors, the C6000’s pipelined architecture provides means to overcome this delay

CPU Load from External Memory DMC ‘C6201 PC mem EMIF 2 SBSRAM   Even providing a zero wait-state off-chip memory, the CPU’s access time for external memory will be upwards of 18 cycles.   Total affect is a 14 cycle delay. (18 cycles less four afforded by C6000’s hardware pipelining.)   C6201 details are shown here. Similar issues affect all C6000 devices (in fact, all high perf  P), but they are manifested differently. For example, the cache in more recent devices mitigate the affect of these delays by keeping often used code and data in faster on-chip memory.   Even providing a zero wait-state off-chip memory, the CPU’s access time for external memory will be upwards of 18 cycles.   Total affect is a 14 cycle delay. (18 cycles less four afforded by C6000’s hardware pipelining.)   C6201 details are shown here. Similar issues affect all C6000 devices (in fact, all high perf  P), but they are manifested differently. For example, the cache in more recent devices mitigate the affect of these delays by keeping often used code and data in faster on-chip memory. Besides cache, what is a better way to increase EMIF throughput? Technical Training Organization T TO

Load from External Memory DMC ‘C6x PC mem EMIF 2 SBSRAM   Unlike the CPU, the EDMA (and DMA) can pipeline-up access through the EMIF delays to achieve single-cycle throughput from zero wait-state external memories.   While the first access may take 14 cycles, subsequent accesses can get down to a single cycle.   Unlike the CPU, the EDMA (and DMA) can pipeline-up access through the EMIF delays to achieve single-cycle throughput from zero wait-state external memories.   While the first access may take 14 cycles, subsequent accesses can get down to a single cycle. EDMA Technical Training Organization T TO

Additional Memory Topics Performance Considerations   Fanout / System   Shared Memory ( HOLD, HOLDA )   Overview of SBSRAM   SDRAM Optimization   C6000 Family EMIF Comparison Technical Training Organization T TO

‘C6201 Bus Fanout H/WMax TypeTop Speed * WaitSize/FanGlueless ASYNC100 MHz Yes16 M/  Yes/No SBSRAM200 MHz No 3 MB Yes SDRAM100 MHz No48 MB Yes   Bus pin drivers rated for 30pf loading   Devices are designed for 45pf loads, but testing equipment cannot guarantee it   Most memory devices present 5pf loads   Total fanout is six memory devices   While this slide is slightly old, the issue remains. Again, IBIS modeling is an excellent way to deal with this issue. Technical Training Organization T TO

System with All Memory Types ‘C6201 SBSRAMSDRAM Flash SRAM FPGA CBT’s and Widebus Transceivers work great CE0 CE2 CE3 Technical Training Organization T TO

Additional Memory Topics Performance Considerations Fanout / System   Shared Memory ( HOLD, HOLDA )   Overview of SBSRAM   SDRAM Optimization   C6000 Family EMIF Comparison Technical Training Organization T TO

Shared Memory Shared Memory ‘C6201 Other  P How can 2  P Share the same memory? Using 3-state buffers. One of the  P or another device arbitrates. Arbiter What is the drawback of using a buffer here? Costs you extra: Speed, Power, Reliability, Money, etc.

Shared Memory Shared Memory ‘C6201 Other  P Arbiter Here’s TI’s solution … Built in buffers!! HOLD

Shared Memory Shared Memory ‘C6201 Other  P Arbiter HOLD When ‘C6x drives HOLDA active: EMIF signals tri-stated CPU continues to execute as long as no off-chip access is needed HOLDA Technical Training Organization T TO

HOLD Status Bits (GBLCTL)  HOLD and HOLDA status  Disable HOLD feature (NOHOLD = 1) HOLDHOLDANOHOLDrsvCLK1ENCLK2ENrsv R, +x RW, +xR, +11RW, +1 R, BUSREQARDY R, +0RW, +0RW, +1 R, +0R, +x rsvrsv± C6711 EMIF GBLCTL Technical Training Organization T TO

Additional Memory Topics Performance Considerations Fanout / System Shared Memory ( HOLD, HOLDA )   Overview of SBSRAM   SDRAM Optimization   C6000 Family EMIF Comparison Technical Training Organization T TO

Access 1 Access 2 Access 3 A1 A2 A3/D1 A4/D2 A5/D3 A6/D4 D5 D6 Access 4 AsynchronousSynchronous A1 D1 A2 D2 A3 D3 A4 D4 Technical Training Organization T TO

Synchronous Burst SRAM (SBSRAM) Access 1 Access 2 Access 3 A1 A2 A3/D1 A4/D2 A5/D3 A6/D4 D5 D6 Access 4 AsynchronousSynchronous A1 D1 A2 D2 A3 D3 A4 D4   Pipelined memory accesses Technical Training Organization T TO

Access 1 Access 2 Access 3 A1 A2 A3/D1 A4/D2 A5/D3 A6/D4 D5 D6 Access 4 AsynchronousSynchronous A1 D1 A2 D2 A3 D3 A4 D4 Synchronous Burst SRAM (SBSRAM)   SBSRAM's pipelines memory accesses   With Burst mode a processor only needs to generate an address every four sequential accesses   Not required by C6000 DSP's as they're fast enough   '0x devices don't use (have) this feature   '1x devices include the burst feature for power savings (only one address pin needs toggling for four sequential accesses) A1 - - /D1 - /D2 A5/D3 - /D4 D5 D6 Burst Technical Training Organization T TO

SBSRAM - Pins 'C6201 AddressEA[N+2:2] DataED[31:0] SBSRAM ClockSSCLK Address Strobe SSADS Output Enable SSOE Write Enable SSWE Chip Enable CE n Byte Enable BE [3:0]   Can be used in all spaces   SSADS asserted for each new address   SSCLK can be 1X or 1/2X CPU clock   Address ADV pin not used (shown on next foil) Technical Training Organization T TO

SBSRAM Considerations  Interface may run at 1x or 1/2x CPU clock  SBSRAM are latent by nature  Read data follows address and control information  EMIF inserts cycles between reads and writes so no conflict occurs  Turn-around penalty (changing directions) is 2 cycles  In general, the first access in a burst sequence will incur 2 cycle setup penalty Technical Training Organization T TO

SBSRAM - Hooking it Up... 'C6201 EA[N+2:2] ED[31:0] SSWE SSOE SSADS SSCLK CEn BE[3:0] SBSRAM A[N:0] D[31:0] WE OE ADV, ADSP ADSC CLK CS BE [3:0] VCC Technical Training Organization T TO

SBSRAM Timing SSADSCE   Data is available 2 cycles after address appears   Data can be accessed at the rate of 1 per cycle SSOE EA/ BE EA1/ BEx EA2EA3 ED D1D2D3 Technical Training Organization T TO

Additional Memory Topics Performance Considerations Fanout / System Shared Memory ( HOLD, HOLDA ) Overview of SBSRAM   SDRAM Optimization   C6000 Family EMIF Comparison Technical Training Organization T TO

Clock InECLKIN Clock OutECLKOUT AddressEA[21:2] DataED[31:0] Write Enable SDWE Row Addr Strobe SDRAS Col Addr Strobe SDCAS A10/RefreshEA12 Chip Enable CE [3:0] Byte Enable BE [3:0] SDRAM - Cheap, Fast, and Easy!   Built-in SDRAM controller   Makes SDRAM easy to use   Glueless interface to SDRAM devices   Works with PC100 SDRAM   High-speed, inexpensive memory   New devices support higher PC1xx SDRAMS Technical Training Organization T TO

SDRAM - Cheap, Fast, and Easy! CLK A[11:0] DQ[15:0] WE RAS CAS CS DQML/H SDRAM0 CLK A[11:0] DQ[15:0] WE RAS CAS CS DQML/H SDRAM1 [15:0] [3:2] [1:0] [31:16] Clock OutECLKOUT AddressEA[13:2] DataED[31:0] Write Enable SDWE Row Addr Strobe SDRAS Col Addr Strobe SDCAS Chip Enable CE [0] Byte Enable BE [3:0] ‘C6x11 EMIF Technical Training Organization T TO

SDRAM Extension Register TCL RD 2RD TRASTWR 6 5 THZP 8 7 RD2DEAC RD2WR DQM 15 TRRD R2W 1617 TRRD WR2DEAC WR 2RD RESERVED   Most SDRAMs will work without programming this register. This is the case for the C6711 DSK.   Program the SDRAM Extension (SDOPT) register to optimize SDRAM performance.   Please refer to the SDRAM applications note (at the TI website) for further details on programming this register. Technical Training Organization T TO

Additional Memory Topics Performance Considerations Fanout / System Shared Memory ( HOLD, HOLDA ) Overview of SBSRAM SDRAM Optimization   C6000 Family EMIF Comparison Technical Training Organization T TO

EMIF Variations Devices 'x01'x02/3/4/5'x11'6712'64x (A)'64x (B) Scheme'0x'1x Bus Width Size (MB) Sync Clocking CPU clk ½ CPU clk ½ CPU clk Independent ECLKIN (  100MHz) Independent ECLKIN ¼ CPU clk 1 / 6 CPU clk CE1 TypesAsync OnlySync & Async Sync Mem Allowed in System Both SDRAM & SBSRAM Either SDRAM or SBSRAM Both SDRAM and SBSRAM All Pipelined SBSRAM Flow thru SBSRAM ZBT SRAM Std Sync FIFO FWFT FIFO

C6201/C6701 Memory Ranges 4M x 8 ASYNC or SBSRAM 2K x 256 Int’l Prog On-chip Peripherals 64K x 8 Int’l Data 0000_ _ _ _0000 CE0 CE1 CE2 CE3 0300_0000 (access as 32-bit only) 4M x 8 ASYNC or SBSRAM (access as 32-bit only) 4M x 8 ASYNC or SBSRAM (access as 32-bit only) 4M x 8 ASYNC or SBSRAM 16M x 8 SDRAM 16M x 8 SDRAM 16M x 8 SDRAM (read access as 8/16/32-bit, write access as 32-bit only) Technical Training Organization T TO

‘C6x01 - MAP 0 vs. MAP 1 CE0 (16M) CE1 (4M) P D 100_ _ Memory CE2 CE3 D 040_ _ Memory CE2 CE3 140_ _ _ _0000 CE0 (16M) CE1 (4M) P Technical Training Organization T TO

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