Analog Circuit Design Techniques at 0.5 V Shouribrata Chatterjee Department of Electrical Engineering, Indian Institute of Technology Delhi

2 Fully integrated 0.5 V analog circuits Gate and body-input OTAs PLL-tuned filter and track-and-hold circuits Operation from 0.45 V to 0.6 V True low-voltage circuits for the nano-scale era Track-and-holds Biasing circuits MasterSlave 1.2 mm Filter PLL OTAs 1 mm Biasing circuits

3 [ITRS'04] Thick Oxide Vdd Thin Oxide Vdd Threshold Technology node [nm] Volts Deep-sub-1 V for nano-scale CMOS devices

4 Latch-up Positive feedback structure if Q 2 switches ON Requires V DD to be more than at least one diode drop

5 Body effect

6

0.5 V OTA design

8 Assuming |V GS - V T | ≈ 0.15 V, |V T | = 0.5 V OTA design challenges 0.15 V 0.5 V 0.65 V 0.8 V V 0.15 V V

9 Basic body-input OTA stage [S. Chatterjee, Y. Tsividis, P. Kinget, ESSCIRC 2004] 0.25 V0.5 V 0.25 V V 0.1 V

10 Two-stage fully-differential body- input OTA Pole splitting using Miller capacitor

11 Micro-photograph Chip prototype 0.18 µm CMOS mixed-signal process: –Standard nMOS and pMOS devices, –High resistivity poly resistors, –MIM capacitors. Die Area: sq. mm Layout

12 Assuming |V GS - V T | ≈ 0.15 V, |V T | = 0.5 V Basic gate-input OTA 0.5 V 0.4 V V 0.4 V 0.25 V 0.1 V

V gate-input OTA gain stage [S. Chatterjee, Y. Tsividis, P. Kinget, ISSCC 2005]

14 Two stage gate-input OTA Common-mode output of first stage is 0.4 V 55 dB gain, 15 MHz GBW, 60 º PM for diff 10pF load 0.25 V 0.4 V

15 Two-stage gate-input fully differential 0.5 V OTA with Miller compensation

16 Setting common-mode voltages for the gate-input OTA 0.4 V R b = 2/3 R i ||R f 0.25 V 0.5 V

Gate-input OTA automatic biasing circuits

18 Error amplifier for biasing 20 kHz GBW for 1 pF load 2 µA current Controlled body voltage sets the amplifier threshold V in V out V out [V] V in [V] [S. Chatterjee, Y. Tsividis, P. Kinget, ISSCC 2005]

19 On-chip biasing circuits V bn generating circuit Level shift biasing circuit (Simplified OTA)

20 OTA dc transfer characteristics and V NR generation V NR generating circuit Replica of OTA stage 1 Input differential voltage [mV] Output diff voltage [V] Increasing V NR

0.5 V body and gate-input OTA measurements

22 Body-input OTA open-loop frequency response DC gain: 52 dB GBW: 2.5 MHz Phase Margin: 45 0 Simulation Measurement Frequency [Hz]

23 Frequency [Hz] Gain [dB] 350 mV (Automatic gain-boosting) 50 mV Increasing gain- boosting bias GBW: 10 MHz Gate-input OTA open-loop frequency response

0.5 V measured performance summary ParameterBody OTAGate OTA Power dissipation [µW]11075 Area [mm 2 ] Load capacitance [pF] (single-ended)20 Offset standard deviation (20 samples) [mV]32 Open-loop DC gain [dB] (diff.)5262/42 Open-loop unity-gain BW [MHz] (diff.) Slew rate [V/µsec] (diff.) Closed-loop unity-gain BW [MHz] (diff.) kHz [dB] kHz [dB]7681 Input ref. 10kHz [nV/sqrt-Hz] (diff.) Input ref. 1MHz [nV/sqrt-Hz] (diff.)8070 Output amp. for 1% THD [mV p-p] (diff.) Closed loop Open loop

0.5 V weak-inversion varactor for frequency tuning

26 Filter tuning challenges at 0.5 V Gm-C MOSFET-C Switching banks of R’s and C’s Varactor-R techniques Gate (0.4 V) Source Drain (0.25 V) Body (V tune ) V gate -V tune or V GB [V] C gs /C ox V GS = 0.15 V V GS = 0.20 V V GS = 0.25 V [S. Chatterjee, Y. Tsividis, P. Kinget, VLSI 2005]

27 Capacitance characteristics V GS [V] C gs /C ox Region of interest for use as weak- inversion varactor Charge Sheet Model Channel doping = 3.5e17/cm 3 V FB = -1 V Increasing V GB from -0.1V to 0.4V

28 5 th order elliptic low-pass filter using tunable integrators Frequency [Hz] Gain [dB] 280 kHz 135 kHz [S. Chatterjee, Y. Tsividis, P. Kinget, ISSCC 2005]

29 Block diagram

30 Chip micrograph 0.18 µm CMOS MIM capacitors High-res resistors Standard V T Triple well devices FilterPLL Biasing circuits OTAs 1 mm

31 Frequency [Hz] Gain [dB] Measured filter response for different supply voltages

32 Filter tuning through the varactor Frequency [Hz] Gain [dB] Notch at 120kHz, -42dB 200kHz, -50dB V B [V] Notch depth (sim.) [dB] Notch depth (meas.) [dB]

33 Filter performance summary at 27C V DD [V] dB cut-off frequency [kHz]135.0 Total current [mA] Noise [µV rms] Input [mV rms] (100kHz / 1% THD)50 In-band IIP 3 [dBV]-5-3 Out-of-band IIP 3 [dBV]3535 Dynamic range [dB] Tuning range [kHz] V tune = V DD V tune = 0.0 V VCO [µV rms] Functionality tested from 5C to 85C at 0.5 V Measured CMRR (10 kHz common mode tone): 65 dB Measured PSRR (10 kHz tone on power supply): 43 dB

0.5 V fully-differential track-and- hold circuit

35 Sampling challenges at 0.5 V Large V DD Small V DD Enough headroom No headroom

36 Basic track-and-hold architecture Voltages on both sides of the switches are signal independent. Signal-independent charge injection. Does this work at a 0.5V power supply? v out v in [Ishikawa, JSSC Dec 89]

37 Differential implementation at 0.5V Gate-input OTA used. Track phase during  1, hold phase during  2. During track phase, pole and zero cancel out to enable fast response. pMOS switches have V T of about 0.5V.

38 Track mode operation Resistors to 0.5V maintain required OTA input CM voltage of 0.4V. To enable better switching, both gate and body of the switch are used. No voltage swing on either side of the switches.

39 Hold mode operation Gate and body of the switch used for better switching. No signal swing on both sides of the switches. OTA input voltages held constant.

V fully-differential OTA [S. Chatterjee, Y. Tsividis, P. Kinget, ISSCC’05, JSSC Dec’05]

V fully-differential OTA [S. Chatterjee, Y. Tsividis, P. Kinget, ISSCC’05, JSSC Dec’05]

V fully-differential OTA [S. Chatterjee, Y. Tsividis, P. Kinget, ISSCC’05, JSSC Dec’05]

V fully-differential OTA [S. Chatterjee, Y. Tsividis, P. Kinget, ISSCC’05, JSSC Dec’05]

44 Design targets 1MHz of sampling rate. 60 dB of signal to noise-distortion range. OTA worst case gain-bandwidth of 20MHz. Worst case slew rate of 6V/µs. Sampling capacitor of 1pF. To be designed using devices with V T V Switches sized to optimize resistance for settling, minimize noise, feedthrough.

45 Test plan: two track-and-holds in cascade CLKA CLKB [Vorenkamp, JSSC Jul 92]

46 Prototype-chip block diagram

47 Track-and-hold chip micrograph 0.25µm CMOS |V t |= 0.6V MIM capacitors Triple-well devices High-resistivity resistors Chip fabrication supported by Philips. Track-and-holds Biasing circuits MasterSlave 1.2mm

48 Some simulated results at 0.5V, 1M-sample/sec Time [sec] Output transient [V] Input at F S /2 x 127/128 Output at F S /2 x 1/128 Input amplitude [dBV] SNDR [dB] 62dB simulated dynamic range

49 Typical time-domain output waveform Time [µsec] Output differential voltage [mV] Re-sampled 25kHz output for a 200mVpp input at 475kHz

50 Measured SNDR Input differential rms [dBV] SNDR [dB]

51 T/H noise analysis and measurements Integrated rms differential input-refd noise: Simulated Noise:200µV RMS OTA GBW:20MHz Measured Noise:188µV RMS OTA GBW:15MHz

52 Measured performance Power supply0.5V Current consumption600µm Sampling rate1Msps Diff. input refd. integrated noise188µV RMS Peak SNDR f IN =50kHz; V in,diff =178mV RMS 60dB Peak SNDR f IN =495kHz; V in,diff =100mV RMS 57dB Hold mode droop rate on diff. output7.6µV/µV Pedestal on diff. output0.8mV Track mode bandwidth3.9MHz

53 Conclusions Developed true low voltage design techniques for 0.5 V analog circuits. 0.5 V gate and body-input OTAs designed - can be used as building blocks. Robust automatic biasing techniques developed. Weak-inversion MOS varactor developed. PLL-tuned 5th-order LPF demonstrated. 0.5 V track-and-hold circuit proposed. Step towards nano-scale circuits.

54 Further reading S. Chatterjee, Y. Tsividis, P. Kinget, “0.5-V Analog Circuit Techniques and Their Application to OTA and Filter Design”, IEEE Journal of Solid State Circuits, Dec. 2005, vol. 40, no. 12, pp S.Chatterjee, P.Kinget, “A 0.5-V 1-Msps Track-and- Hold Circuit with 60-dB SNR”, IEEE Journal of Solid State Circuits, Apr. 2007, vol. 42, no. 4, pp K. Pun, S. Chatterjee, P. Kinget, “A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator with a Return-to-Open DAC”, IEEE Journal of Solid State Circuits, Mar. 2007, vol. 42, no. 3, pp