ECE : Nanoelectronics Prof. Virginia Ayres Electrical & Computer Engineering Michigan State University

VM Ayres, ECE802, F13 Lecture 01, 29 Aug 13 Course:ECE : Nanoelectronics Time:Tuesday and Thursday, 8:30-9:50 am Place:Room 2245 Engineering Building Instructor:Prof. Virginia Ayres, Department of Electrical and Computer Engineering Website: Telephone: Office:C-104 Engineering Research Complex; Lab, C-22 Office Hours:Evenings 2 days before homework is due, in Engineering Library 6:00-9:00 pm

VM Ayres, ECE802, F13 Grading: Midterm (take-home)150 pts. Final (take home)150 pts Homework:50 pts Total:350 pts Final dates (anticipated): Office Hours: Official Tuesday 10 Dec 13: 7:45-9:45 in Room 2245 EB Final Exam due: Thursday 12 Dec13, to ECE Office, by 4:30 pm

VM Ayres, ECE802, F13 Textbooks (amazon.com): 1. Electronic Transport in Mesoscopic Systems, Supriyo Datta, Cambridge University Press 1997 $ Physical and Electronic Properties of Carbon Nanotubes, R. Saito, G. Dresselhaus, M.S. Dresselhaus, Imperial College Press 1998 $24 Prerequisite:ECE874: Physical Electronics or equivalent

VM Ayres, ECE802, F13 Why Study Nanoelectronics Paraphrasing from Wikipedia: Nanoelectronics refers to the use of nanotechnology in electronic components. The term covers a diverse set of devices and materials, with the common characteristic that one or more elements are so small that quantum mechanical properties need to be considered extensively. Some of these candidates include: single electron transistors, two-dimensional quantum wells, one dimensional nanotube/nanowire FETs, hybrid molecular/semiconductor electronics, and advanced molecular electronics. Even state-of-the-art silicon CMOS technology generations, such as the 22nm node, are within this regime.

VM Ayres, ECE802, F13 Nanoelectronics is considered as a disruptive technology because present candidates are significantly different from traditional transistors. If your career choice involves electronics, it is important to acquire both fundamental understanding and a practical set of the right working tools prior to a disruptive technology insertion. When a disruptive technology insertion happens (transistors themselves were one), a downside is that jobs are lost BUT the upside is that an amazing career experience belongs to those who can run with it.

VM Ayres, ECE802, F13 ECE 802: Nanoelectronics is a rigorous development of the right techniques for working with electronics that include elements such as quantum wells, semiconductor nanowires, carbon nanotubes, graphene, organic nanofibers or organic single molecules. Let’s look at the outline of course topics.

VM Ayres, ECE802, F13 Transport in 2-Deg and 1-Deg Semiconductor Nanoelectronics Scaling relations in reduced dimensionalities Density of States in reduced dimensionalities Quantum Transport in reduced dimensionalities Quantum Transport in a single electron transistor Datta Chps Examples of Transport in 2-Deg  Quantum Hall Effect  Localization  Double Barrier Tunnelling Datta Chps. 04, 05, 06 Transport in Carbon Nanoelectronics Bond hybridization derivation: sp1, sp2, sp3 Graphene Density of States Transport in Graphene Carbon nanotube (CNT) structure CNT Density of States Transport in CNTs Phonons in CNTs Dresselhaus Chps. 02, 03, 08 Transport in Organic 1-Deg Organic molecular electronics systems Solitons and transport in molecular electronics Transport in electrospun nanofibers (electronic textiles) Ayres Notes and References Outline of Course Topics:

VM Ayres, ECE802, F13 Scales and Metrics

VM Ayres, ECE802, F13 Fig. 01 in Datta: Scales 22 nm node

VM Ayres, ECE802, F13 22 nm node Fig. 01 in Datta: Scales textbooks Unit cell

VM Ayres, ECE802, F13 22 nm node Fig. 01 in Datta: Scales Chp. 01 in Datta

VM Ayres, ECE802, F13 WikiAnswers: 45 nm technology refers to size of the transistors in a chip. A technology node is defined as the ground rules of a process governed by the smallest feature printed in a repetitive array. The half-pitch of first-level interconnect dense lines is most representative of the DRAM technology level required for the smallest economical chip size. This is currently chosen as the dimension that defines a technology node. It is, however, anticipated that in the future, the half-pitch dimensions of either metal or polysilicon interconnections of microprocessors (MPUs) and ASIC devices may rival or even become smaller than the corresponding half-pitch of DRAM. The half-pitch dimension however, may not represent the smaller feature of the chip. For instance, for logic devices, such as MPUs, physical bottom gate length represents the smallest feature. Nevertheless, the technology node definition remains tight to the half-pitch indicator as defined above. see this ref. for more DRAM: Dynamic random-access memory

VM Ayres, ECE802, F13 From Wikipedia, the free encyclopedia 22 Nanometer The 22 nanometer (22 nm) is the CMOS process step following the 32 nm process in CMOS semiconductor device fabrication. The typical half-pitch (i.e., half the distance between identical features in an array) for a memory cell using the process is around 22 nm. It was first introduced by semiconductor companies in 2008 for use in memory products, while first consumer-level CPU deliveries started in April The ITRS 2006 Front End Process Update indicates that equivalent physical oxide thickness will not scale below 0.5 nm (about twice the diameter of a silicon atom), which is the expected value at the 22 nm node. This is an indication that CMOS scaling in this area has reached a wall at this point, possibly disturbing Moore's law. On the ITRS roadmap, the successor to 22 nm technology will be 14 nm technology. On August 18, 2008, AMD, Freescale, IBM, STMicroelectronics, Toshiba, and the College of Nanoscale Science and Engineering (CNSE) announced that they jointly developed and manufactured a 22 nm SRAM cell, built on a traditional six-transistor design on a 300 mm wafer, which had a memory cell size of just 0.1 μm2.[1] The cell was printed using immersion lithography.[2] SRAM: Static random-access memory

VM Ayres, ECE802, F13 From Wikipedia, the free encyclopedia 22 Nanometer SCALES: On August 18, 2008, AMD, Freescale, IBM, STMicroelectronics, Toshiba, and the College of Nanoscale Science and Engineering (CNSE) announced that they jointly developed and manufactured a 22 nm SRAM cell, built on a traditional six-transistor design on a 300 mm wafer, which had a memory cell size of just 0.1 μm2.[1] The cell was printed using immersion lithography.[2] A typical SRAM cell is made up of six MOSFETs. Each bit in an SRAM is stored on four transistors (M1, M2, M3, M4) that form two cross-coupled inverters. This storage cell has two stable states which are used to denote 0 and 1. Two additional access transistors serve to control the access to a storage cell during read and write operations. Intel’s 45 nm SRAM cell sizeIntel’s 45 nm SRAM cell size (the test chip that was used for today’s 45 nm processors) is μm 2. New 22 nm SRAM cell sizeNew 22 nm SRAM cell size (22 nm processor) is 0.1 μm 2.

VM Ayres, ECE802, F13 From Wikipedia, the free encyclopedia 22 Nanometer SCALING means something different: The ITRS 2006 Front End Process Update indicates that equivalent physical oxide thickness will not scale below 0.5 nm (about twice the diameter of a silicon atom), which is the expected value at the 22 nm node. This is an indication that CMOS scaling in this area has reached a wall at this point, possibly disturbing Moore's law. ECE 474: Electric field is proportional to distance: closer to charge source = stronger field. Charges creates E (y) in channel. Stronger field E (y) => v sat (y) negatively impacts device performance. ECE 875: Goal: scale device = reduce all dimensions but keep E field constant E = 10 5 N/C in Si Average e- velocity

VM Ayres, ECE802, F13 Adjust device parameters to keep E field constant: Shrink physical parameters by 1/k Shrink all batteries by 1/k Increase substrate doping by k to adjust surface potential ECE875: For Constant E field = “constant field”

VM Ayres, ECE802, F13 Adjust device parameters to keep E field constant: Shrink physical parameters by 1/k Shrink all batteries by 1/k Increase substrate doping by k to adjust surface potential Constant E field = “constant field” Moore’s law problem: tunnelling across the oxide layer d

VM Ayres, ECE802, F13 Fig. 01 in Datta: Metrics that describe Scales Nano nature: Wave particle-duality of carriers (electrons)

VM Ayres, ECE802, F13 Fig. 01 in Datta: Metrics that describe Scales Nano nature: Wave particle-duality of carriers (electrons) Particle-like Wave-like