TRIO-CINEMA 1 UCB, 2/08/2010 STEIN Intro Davin Larson Space Sciences Laboratory University of California, Berkeley

TRIO-CINEMA 2 UCB, 2/08/2010 STEIN (SupraThermal Electron, Ion, Neutral ) sensor Energy range: ~2-300 keV Resolution: ~ 1keV FWHM Field of view ~15º x70º

TRIO-CINEMA 3 UCB, 2/08/2010 CINEMA (Cubesat for Ions, Neutrals, Electrons, MAgnetic fields)

TRIO-CINEMA 4 UCB, 2/08/2010 Energy-Angle Response for Edge Pixels

TRIO-CINEMA 5 UCB, 2/08/2010 Energy-Angle Response for Middle Pixels

TRIO-CINEMA 6 UCB, 2/08/2010 Center Pixel Response (Electrons)Edge Pixel Response (Electrons) Deflection Voltage 4 kV kV Left SweepRight Sweep Symmetric response for ions Neutrals measured in center pixel – cleanly separated for energies below ~15-20 keV Logarithmic voltage sweep with ten steps from 600V to 4 kV is optimal for covering phase space. Need positive and negative sweeps to get all angles, so 20 voltage steps desired.

TRIO-CINEMA 7 UCB, 2/08/2010 Estimation of Circuit board area

TRIO-CINEMA 8 UCB, 2/08/2010 STEIN Preamp Schematic

TRIO-CINEMA 9 UCB, 2/08/2010 STEIN Preamp Schematic

TRIO-CINEMA 10 UCB, 2/08/2010 STEIN Preamp Schematic

TRIO-CINEMA 11 UCB, 2/08/2010 STEIN Shaper Chain (1 of 4)

TRIO-CINEMA 12 UCB, 2/08/2010 STEIN – DACs / Actel schematic

TRIO-CINEMA 13 UCB, 2/08/2010 END of PRESENTATION

TRIO-CINEMA 14 UCB, 2/08/2010 STEIN Testing New deflector plates Built and installed (1 of 2) Test (planned) on 2010/1/9 Replace parallel plates with Series of blades

TRIO-CINEMA 15 UCB, 2/08/2010 STEIN STEIN ETU on Manipulator

TRIO-CINEMA 16 UCB, 2/08/2010 STEIN Electron Calibration Setup yaw angle Pen-ray UV Lamp -V Vacuum chamber (grounded) Quartz window VD Cr Layer Delrin Insulator STEIN Mounted on 3-axis Manipulator Electron Beam D0 D3 D2 D1

TRIO-CINEMA 17 UCB, 2/08/2010 Solid State Detector Basics +35 V ~200A Al ~200A Poly Si 300 micron thick detector Outside at bias Voltage np Example: 3.6 keV Particle strikes detector guard ring It takes 3.6 eV to make one electron-hole pair Total charge produced is: N = 3600 eV /3.6eV = 1000 electrons = 1.6e-16C Output PH is proportional to deposited energy! Charge Time Voltage CSA Shaper 2ns 2us PH Avg signal in black Real signal in red The shaper circuit averages out the “noise” Minimize distance -+

TRIO-CINEMA 18 UCB, 2/08/2010 Solid State Detector Basics (Cont) 300 micron thick detector Time Voltage Shaper 2us PH The shaper circuit averages out the “noise” Shaper Time Voltage 2us Thresh ADC FPGA (logic) Convert signal occurs when THRESH is high and PD passes through zero Memory Signal DAC Thresh Convert Read Convert PD Signal Zero crossing Comparator Differentiator

TRIO-CINEMA 19 UCB, 2/08/2010 single 4keV electron 2 simultaneous 4 keV electrons

TRIO-CINEMA 20 UCB, 2/08/2010 Response to Electron gun sweep Time  ADC channel Singles Doubles Triples Count rate during electron gun sweep not symmetric Benefits of automation: It is extremely useful to collect data continuously and plot history of measurements. Note slight increase in electron beam intensity and hysteresis effect between ramp up and ramp down.

TRIO-CINEMA 21 UCB, 2/08/2010

TRIO-CINEMA 22 UCB, 2/08/2010 Deflector YAW angle 15 keV constant electron beam

TRIO-CINEMA 23 UCB, 2/08/2010 Yaw angle D0 D3 D2 D1 Scattered e-’s Detector response vs Yaw angle D0 D3 D2 D1 Total counts

TRIO-CINEMA 24 UCB, 2/08/2010 Agenda AGENDA Overview Requirements Design Development Plan Issues

TRIO-CINEMA 25 UCB, 2/08/2010 Overview Processor Board Combined LVPS/Logic EXAMPLE ONLY

TRIO-CINEMA 26 UCB, 2/08/2010 Requirements EXAMPLE ONLY

TRIO-CINEMA 27 UCB, 2/08/2010 PIC – UHF (UART) PIC – EPS ( I 2 C ) PIC – SD card (SPI) PIC – FPGA (SPI & I 2 C) SD CARD FPGA – Tx (bitsteam) FPGA – STEIN (CDI) FPGA – MAGIC (SPI) Design Data Flow Specifications Tx : 1 Mbps continuous SDCARD : 1.28 Mbps Write, 1 Mbps Read (min) STEIN: 16 bits/event, 80KHz events = 1.28Mbps MAGIC: 20 bits x 20 Hz x 3 axes =.001 Mbps UHF: Mbps EXAMPLE ONLY

TRIO-CINEMA 28 UCB, 2/08/2010 Development Plans Development Pumpkin Development Board + Laptop PC MPLAB30 “C” Compiler, Simulator, Debuggers Subversion (SVN) for storing source code and documents GSE Laptop running GSEOS FSW Developed in phases: –CPU/Mother Board Only –CPU/Mother Board + [EPS, Batt, UHF, IIB] –CPU/Mother Board + [EPS, Batt, UHF, IIB] + [HVPS,STEIN, MAG] Verification Matrix Provides Status of Requirements Comprehensive Performance Test on Development Board Load into Flight System Joins CINEMA Test Flow and Quality reporting EXAMPLE ONLY

TRIO-CINEMA 29 UCB, 2/08/2010 Issues CPU Floating Point Mult/Div/Add performance#’s needed Memory Very Small (especially 2K DMA area) Pumpkin RTOS not useful for FSW EXAMPLE ONLY