© H. Heck 2008Section 4.41 Module 4:Metrics & Methodology Topic 4: Recovered Clock Timing OGI EE564 Howard Heck

Recovered Clock Timing EE 564 © H. Heck 2008 Section 4.42 Where Are We? 1.Introduction 2.Transmission Line Basics 3.Analysis Tools 4.Metrics & Methodology 1.Synchronous Timing 2.Signal Quality 3.Source Synchronous Timing 4.Recovered Clock Timing 5.Design Methodology 5.Advanced Transmission Lines 6.Multi-Gb/s Signaling 7.Special Topics

Recovered Clock Timing EE 564 © H. Heck 2008 Section 4.43 Why Another Clocking Scheme? 2 Problems of interest:  What do we do when we’re trying to communicate between devices that don’t have a “common clock?”  e.g. an external device?  Both devices will have clocks, but those clocks will not have a known phase relationship. We have to deal with it.  What do we do when we’re sending data at multi-GTs speeds, while low cost system clocks operate below 1 GHz? In such cases, we typically do not send an explicit clock signal to the devices at all. Instead, we “extract” the clock information from the data stream.

Recovered Clock Timing EE 564 © H. Heck 2008 Section 4.44 Contents Goal Timing Relationships & Equations Example System & Operation Summary

Recovered Clock Timing EE 564 © H. Heck 2008 Section 4.45 Goals Our goal is to establish and maintain a desired phase relationship between DCLK and RCLK in order to ensure that we successfully transmit and receive data. The phase relationship between the system clock inputs cannot be predetermined or directly controlled, so we must do it locally on each device. We can also use the local adjustment circuitry to generate high frequency local clocks for controlling the data transfer.

Recovered Clock Timing EE 564 © H. Heck 2008 Section 4.46 Data-Clock Phase Relationship The receiver clock recovery circuitry attempts to center the receiver clock in the data eye.  i.e. maintain a 90  offset between B and RCLK. Accounting for driver and interconnect delay, the desired phase relationship between DCLK and RCLK is: 90° RCLK B T CO DCLK A T flight T  Jitter on the driver, receiver, and interconnect, and frequency differences between will degrade the phase relationship (i.e. setup/hold margin) between B and RCLK.

Recovered Clock Timing EE 564 © H. Heck 2008 Section 4.47 Phase Relationship - Setup Worst case setup case:  T CO & T flight increase  DCLK pushes out  RCLK pulls in The corresponding DCLK to RCLK relationship is shown below: T co,max and T flight,max are taken over M cycles. They include ISI, crosstalk, SSO, etc. T pushout (DCLK) is the maximum pushout of the driver clock after M cycles w.r.t. to the edge at the 1 st cycle. T pullin (RCLK) is the maximum pullin of the receiver clock after M cycles w.r.t. to the edge at the 1 st cycle. RCLK B DCLK A T pushout (DCLK) T CO,max = T = T co + T+ T co,pushout T flight,max = T = T flight + T flight,pushout T pullin (RCLK) 90° - (T flight,pushout + T CO,pushout ) - T pullin (RCLK) - T pushout (DCLK)

Recovered Clock Timing EE 564 © H. Heck 2008 Section 4.48 Phase Relationship - Hold Worst case setup case:  T CO & T flight decrease  DCLK pulls in  RCLK pushes out The corresponding DCLK to RCLK relationship is shown below: T co,min and T flight,min are taken over M cycles. They include ISI, crosstalk, SSO, etc. T pullin (DCLK) is the maximum pullin of the driver clock after M cycles w.r.t. to the edge at the 1 st cycle. T pushout (RCLK) is the maximum pushout of the receiver clock after M cycles w.r.t. to the edge at the 1 st cycle. RCLK B DCLK A T pullin (DCLK) T CO,min = T CO - T CO,pullin T flight,min = T flight -T flight,pullin T pushout (RCLK,) 90° - (T flight,pullin + T CO,pullin ) - T pullin (DCLK,) - T pushout (RCLK)

Recovered Clock Timing EE 564 © H. Heck 2008 Section 4.49 Setup & Hold Equations (Skipping the derivation) Define Tx, Rx, and flight time jitter:  Tx jitter (  T TX,max ) is maximum phase uncertainty of transmitted data including variation in the local clock.  Rx jitter (  RX,max ) is maximum phase uncertainty of received data including variation in the local clock.  Flight time jitter (  lightmax ) is maximum phase uncertainty of the interconnect flight time  All quantities are positive for setup, negative for hold Keeps with previous conventions  Ideal phase relationship between data edge at the receiver input and RCLK. Here are the simplified setup & hold equations:

Recovered Clock Timing EE 564 © H. Heck 2008 Section Example Extracted Clock System System clock ( SCLK ) is multiplied by N to produce higher frequency at C. The local clock is phase aligned to the output of the loop filter, producing local clock, DCLK. DCLK is divided by N, and the phase of D is compared to the system clock, SCLK, producing E. Phase error is averaged over several clock cycles by the loop filter and fed back to the clock adjustment circuit ( F ).

Recovered Clock Timing EE 564 © H. Heck 2008 Section Example Extracted Clock System (2) The feedback loop described on the previous slide is designed to lock DCLK to an exact multiple of SCLK, providing a stable high frequency clock for the transmitter. DCLK controls the latching of data to the transmitter ( A ). The data bit travels down the line to the receiver ( B ).

Recovered Clock Timing EE 564 © H. Heck 2008 Section Example Extracted Clock System (3) Data at B is latched by RCLK, which has the same frequency as DCLK. RCLK may or may not have the same system clock source as DCLK. The delay element shifts RCLK 90  out of phase from B to center the clock in the data bit, with adjustment by the phase comparator/filter/clock adjust loop. Note that the loop time constant is several cycles, so it does not correct high frequency phase deviations.

Recovered Clock Timing EE 564 © H. Heck 2008 Section Question What requirement does the periodic clock adjustment place on the operation of a channel that uses an extracted clock?

Recovered Clock Timing EE 564 © H. Heck 2008 Section References S. Hall, G. Hall, and J. McCall, High Speed Digital System Design, John Wiley & Sons, Inc. (Wiley Interscience), 2000, 1 st edition. W. Dally and J. Poulton, Digital Systems Engineering, Cambridge University Press, R. Poon, Computer Circuits Electrical Design, Prentice Hall, 1 st edition, H.B.Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison Wesley, H. Johnson and M. Graham, High Speed Digital Design: A Handbook of Black Magic, PTR Prentice Hall, S. Dabral and T. Maloney, Basic ESD and I/O Design, John Wiley and Sons, New York, 1998.

Recovered Clock Timing EE 564 © H. Heck 2008 Section Appendix: Extracted Clock Equation Derivation

Recovered Clock Timing EE 564 © H. Heck 2008 Section Clock Drift Assuming DCLK is updated every M cycles, the phase error quantifies how much the M th DCLK edge deviates from the placement of the M th RefCLK edge. Deterministic noise is caused by sources such as power supply switching, temperature variation, bus noise, and spread spectrum clocking. Gaussian noise is random, which noise, not correlated to any specific source, and will tend to average zero over time.

Recovered Clock Timing EE 564 © H. Heck 2008 Section Clock Drift & Adjustment Variations in flight time and driver delay degrade the phase relationship, and therefore the setup/hold window. Both clocks drift with time, and are adjusted periodically, depending on PLL bandwidth, clock extraction circuits, and T co and T flight variations. Interconnect variations tend to be higher frequency, and are not compensated by the clock extraction circuits. Cycles(N) Hold RequirementHold side margin Setup Requirement Setup side Margin N=1 N=M N=2M N=P High Frequency Interconnect Noise Low frequency drift between Dclk and Rclk

Recovered Clock Timing EE 564 © H. Heck 2008 Section Data Path Delay [8.3.4]

Recovered Clock Timing EE 564 © H. Heck 2008 Section Clock Path Delay [8.3.5] [8.3.6] Phase difference, T  is: T  is the phase error at calibration ( N =1).

Recovered Clock Timing EE 564 © H. Heck 2008 Section Setup Loop [8.3.7]

Recovered Clock Timing EE 564 © H. Heck 2008 Section Setup Equation Starting with the loop equation: [8.3.7] Define the initial phase offset, T  : [8.3.8] [8.3.9] Simplify the loop equation: [8.3.10]

Recovered Clock Timing EE 564 © H. Heck 2008 Section Setup Equation #2 Define worst case transmitter and flight times for the setup case: Simplify the loop equation: [8.3.11]

Recovered Clock Timing EE 564 © H. Heck 2008 Section Setup Equation #3 Define worst case transmitter, receiver, and flight time variation: Rewrite the loop equation: [8.3.16] [8.3.14] [8.3.13] [8.3.12] Maximum data signal pushout w.r.t. refCLK over M cycles. Minimum pull-in of RCLK w.r.t. refCLK over M cycles. Maximum flight time variation over M cycles. [8.3.15] Minimum phase relationship between data edge at the receiver input and RCLK..

Recovered Clock Timing EE 564 © H. Heck 2008 Section Hold Loop [8.3.17]

Recovered Clock Timing EE 564 © H. Heck 2008 Section Hold Equation Starting with the loop equation: [8.3.17] Use the phase relationship: [8.3.19] [8.3.9] [8.3.18] Recall:

Recovered Clock Timing EE 564 © H. Heck 2008 Section Hold Equation #2 Work with the loop equation: [8.3.18] [8.3.20]

Recovered Clock Timing EE 564 © H. Heck 2008 Section Hold Equation #3 [8.3.20] Define: [8.3.24] [8.3.23] [8.3.22] [8.3.21] Minimum data signal pullin w.r.t. refCLK over M+1 cycles. Maximum pushout of RCLK w.r.t. refCLK over M cycles. Minimum flight time variation over M+1 cycles. Maximum phase relationship between data edge at the receiver input and RCLK..

Recovered Clock Timing EE 564 © H. Heck 2008 Section Hold Equation #4 [8.3.25] Finally: