ELEC 6270 Low power design of Electronic Circuits Advisor: Dr.Vishwani Agrawal Student: Chaitanya Bandi.

Slides:

Advertisements

Similar presentations

Course: Low power design of electronic circuits Student: Ahmed Faraz.

Advertisements

Khaled A. Al-Utaibi  Clock Generator Functions  Crystal Oscillator  8284 Pins  8284 Interfacing to the 8086  RC Circuit Charging.

9/15/05ELEC / Lecture 71 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter CMOS INVERTER.

5/9/2015 A 32-bit ALU with Sleep Mode for Leakage Power Reduction Manish Kulkarni Department of Electrical and Computer Engineering Auburn University,

EE435 Final Project: 9-Bit SAR ADC

The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering ECE122 Lab 4: VTC & Power.

ECE 3130 – Digital Electronics and Design Lab 4 VTC and Power Consumption Fall 2012 Allan Guan.

Fall 06, Sep 19, 21 ELEC / Lecture 6 1 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic.

Logical Effort Section Problems: P6.2 Compute the oscillation frequency of a seven-stage ring oscillator using 0.18 micron technology. Does.

Introduction to CMOS VLSI Design Lecture 18: Design for Low Power David Harris Harvey Mudd College Spring 2004.

Timing Analysis Timing Analysis Instructor: Dr. Vishwani D. Agrawal ELEC 7770 Advanced VLSI Design Team Project.

Low Voltage Sequential Circuit With a Ring Oscillator Clock ELEC 6270 Low power design of Electronic Circuits Spring, 2009 Presented by Mridula Allani.

S. Reda EN160 SP’08 Design and Implementation of VLSI Systems (EN1600) Lecture 14: Power Dissipation Prof. Sherief Reda Division of Engineering, Brown.

Week 7a, Slide 1EECS42, Spring 2005Prof. White Week 7a Announcements You should now purchase the reader EECS 42: Introduction to Electronics for Computer.

REDUCED POWER SHIFT REGISTER WITH MULTIPHASE CLOCKS ELEC 6270 Kannan Govindasamy.

Dec. 6, 2005ELEC Glitch Power1 Low power design: Insert delays to eliminate glitches Yijing Chen Dec.6, 2005 Auburn university.

Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 12 1 ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Pass Transistor Logic: A Low Power.

December 1, 2005 ELEC Project Presentation 1 Dual-Voltage Supply for Power Reduction ELEC 6970 – Low Power Design Project Presentation by Muthubalaji.

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 11: Logical Effort (1/2) Prof. Sherief Reda Division of Engineering, Brown.

11/5/2004EE 42 fall 2004 lecture 281 Lecture #28 PMOS LAST TIME: NMOS Electrical Model – NMOS physical structure: W and L and d ox, TODAY: PMOS –Physical.

Nov. 29, 2005 ELEC Class Presentation 1 Reducing Voltage Supply Jins Davis Alexander.

Lecture #24 Gates to circuits

Characterization of a CMOS cell library for low-voltage operation

11/29/2007ELEC Class Project Presentation1 LOW VOLTAGE OPERATION OF A 32-BIT ADDER USING LEVEL CONVERTERS Mohammed Ashfaq Shukoor ECE Department.

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 13: Power Dissipation Prof. Sherief Reda Division of Engineering, Brown.

Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 13 1 ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Pseudo-nMOS, Dynamic CMOS and Domino.

10/20/05ELEC / Lecture 141 ELEC / (Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits.

Lecture 13, Slide 1EECS40, Fall 2004Prof. White Lecture #13 Announcements You should now purchase the reader EECS 40: Introduction to Microelectronics,

Copyright Agrawal, 2007 ELEC6270 Fall 07, Lecture 6 1 ELEC 5270/6270 Fall 2007 Low-Power Design of Electronic Circuits Dynamic Power: Device Sizing Vishwani.

Digital Integrated Circuits© Prentice Hall 1995 Inverter THE INVERTERS.

Practical Aspects of Logic Gates COE 202 Digital Logic Design Dr. Aiman El-Maleh College of Computer Sciences and Engineering King Fahd University of Petroleum.

The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering ECE122 Lab 4: VTC & Power.

Low Power Architecture and Implementation of Multicore Design Khushboo Sheth, Kyungseok Kim Fan Wang, Siddharth Dantu ELEC6270 Low Power Design of Electronic.

CMOS Schmitt Trigger Test Circuit Mitchell Belser, P.E. Visiting Instructor Department of Computer Engineering Jackson State University

Electronic Circuit Diagrams

Module 2 : Behavioral modeling TOPIC : Modeling a Digital pulse UNIT 1: Modeling and Simulation.

A GHz Fourth-Harmonic Voltage-Controlled Oscillator in 130nm SiGe BiCMOS Technology Yang Lin and David E. Kotecki Electrical and Computer Engineering.

Minimum Energy Sub-Threshold CMOS Operation Given Yield Constraints Max Dreo Vincent Luu Julian Warchall.

Digital Electronics 2 - Transistors Introduction to CAD Naehyuck Chang

Spring 2010, Mar 10ELEC 7770: Advanced VLSI Design (Agrawal)1 ELEC 7770 Advanced VLSI Design Spring 2010 Gate Sizing Vishwani D. Agrawal James J. Danaher.

Floyd, Digital Fundamentals, 10 th ed Digital Fundamentals Tenth Edition Floyd © 2008 Pearson Education Chapter 1.

16 Bit Logarithmic Converter Tinghao Liang and Sara Nadeau.

OUT IN LS Gnd +5 Figure 1: (a) Logic Level Measurement (Measure voltage at OUT node). (b) Power Supply Wiring.

ELEC Digital Logic Circuits Fall 2015 Delay and Power Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering.

CMOS 2-Stage OP AMP 설계 DARK HORSE 이 용 원 홍 길 선

CMOS OUTLINE » Fan-out » Propagation delay » CMOS power consumption.

Power-Optimal Pipelining in Deep Submicron Technology

THE CMOS INVERTER.

ECE 3130 Digital Electronics and Design

Very low voltage 16-bit counter in high leakage static CMOS technology

Estimate power saving by clock slowdown for s5378 in 180nm and 32nm CMOS Chao Han ELEC 6270.

KS4 Electricity – Electronic systems

KS4 Electricity – Electronic systems

Sequential logic circuits

Digital Computer Electronics TTL

Analytical Delay and Variation Modeling for Subthreshold Circuits

Reduced Voltage Test Can be Faster!

332:479 Concepts in VLSI Design Lecture 24 Power Estimation

Elec 2607 Digital Switching Circuits

OUTLINE » Fan-out » Propagation delay » CMOS power consumption

Design of benchmark circuit s5378 for reduced scan mode activity

MCP Electronics Time resolution, costs

Power Reduction Technique

KS4 Electricity – Electronic systems

32 BIT PARALLEL LOAD REGISTER WITH CLOCK GATING

Lecture 7: Power.

ELEC 7770 Advanced VLSI Design Spring 2012 Gate Sizing

LS00 3 IN OUT Gnd Figure 1: (a) Logic Level Measurement (Measure voltage at OUT node). (b) Power Supply Wiring.

Agenda Lecture Content: Combinatorial Circuits Boolean Algebras

Presentation transcript:

ELEC 6270 Low power design of Electronic Circuits Advisor: Dr.Vishwani Agrawal Student: Chaitanya Bandi

Index Ring Oscillator Operation Tools Used Schematic Power and Frequency Versus Voltage (Expected and Observed) for different values of N (where N is the number of gates). References

Ring Oscillator A ring oscillator is a device composed of an odd number of NOT gates whose output oscillates between two voltage levels, representing 1 and 0. The NOT gates, or inverters, are attached in a chain; the output of the last inverter is fed back into the first

Tools Used Design Architect: To create and Edit the Schematic Eldo: To find the Frequency of oscillations and Average Power consumed

Schematic from Design Architect Ringin: input pin to initialize the oscillations Ringout: output pin from at which oscillations are observed

Vdd= 5 v Vdd= 4v Simulation results of the Ring oscillator from ELDO for N=11

Vdd = 3 v Vdd=2v

Vdd= 1 v Vdd =.9 v

Vdd=.85v Vdd=.815

Rise time & Fall Time Vs Voltage Vdd (volts)Rise timefall time 50.08ns0.07ns 40.10ns0.07ns 30.11ns0.1ns 20.2ns0.1ns 10.8ns0.34ns n0.76ns ns0.82ns ns1.83ns N=11 The rise times and fall times of the oscillator increases with a decrease in supply voltage which indicates that the delay of the gates increases with a decrease in the supply voltage.

For N=11, Power & Freq Vs Voltage Vdd (Volts)FrequencyPower 5826MHz3.382mW 4698MHz1.7mW 3562MHz702uW 2367MHz187uW 164.9MHz6uW MHz1.18uW

For N=19, Power & Freq Vs Voltage Vdd (Volts)FrequencyPower 5826MHz6.61mW 4698MHz2.93mW 3562MHz1.212mW 2367MHz323uW 164.9MHz10.36uW MHz2.038uW

For N=5, Power & Freq Vs Voltage Vdd(Volts)FrequencyPower 52.1GHz1.57mW GHz0.788mW 31.43GHz330uW 2.952GHz87uw 1168MHz2.89uW MHz.54uW

N=19,11,5 Power Vs Voltage X-Axis: Voltage(Volts) Y-Axis: Power(uW)

N=19,11,5 Frequency Vs Voltage X-Axis: Voltage(Volts) Y-Axis: Frequency(MHz)

Power Vs number of gates(N) As the number of gates increases the Average power increases proportionally. X-axis: Number of gates Y-axis: Average Power

Expected Power and Frequency 1)Power α f* (Vdd) ^2 ; where f is the observed frequency 2) Delay of Each gate α (Vdd)/(Vdd-Vth) Vth = 0.54v for tsmc035 technology

Average power & Expected Power N=11 Vdd(volts)average powerExpected Power mW mW 1.845mW 3.711mW 0.846mW 2.191mW mW 16.33uW 10.67uW uW 2.322uW nW 11.5nW

Average power & Expected Power N=19 Vdd(volts)Average PowerExpected Power 56.61mW 42.93mW 3.600mW mW 1.571mW 2323uW uW uW 20.43uW uW 4.37uW

Average power & Expected Power N=5 Vdd(volts)Average PowerExpected Power 51.57mW mW 1.087mW 3330uW uW 287uw uW 12.89uW 25.12uW uW 6.33uw

Observed & Expected Frequency N=11 VDD (Volts)frequencyExpected Frequency GHz GHz1.34Ghz GHz1.277Ghz 2.627GHz1.136Ghz 1.109GHz.716GHz GHz.568GHz MHz.155GHz

Observed & Expected Frequency N=19 Vdd(Volts)FreqExpected Freq 5826MHz 4698MHz800.9MHz 3562MHz759.3MHz 2367MHz675.8MHz 164.9MHz425.9MHz MHz337.7MHz

Observed & Expected Frequency N=5 VDD(volts)FreqExpected Freq 52.1GHz GHz2.036GHz 31.43GHz1.93GHz 2.952Ghz1.718GHz 1168MHz1.08GHz MHz858MHz

Observations If the Vdd is changed from 5v to 0.85V there is a power reduction of about 99.9%, but the frequency of oscillations is decreased by 76%. The Frequency of oscillations decreases as the number of gates in the oscillator increases. The Power consumption increases in proportion to the number of gates in the oscillator. The Observed frequencies are lesser than the expected frequencies due to large delays in the gates at low operating voltages.

References: 1.Fall 2007: ELEC6270 Low Power Design Electronics Class Slides from Dr. Agrawal 2.Fall 2007: ELEC6250 Computer Aided Design of Digital Logic Circuits Lectures 4,23 from Dr. Nelson’s Class slides. 3.