Introduction to IC Test Tsung-Chu Huang (黃宗柱) Department of Electronic Eng. Chong Chou Institute of Tech. Email: tch@dragon.ccut.edu.tw 2004/04/19

Syllabus & Chapter Precedence Introduction Modeling Logic Simulation Fault Modeling Fault Simulation Testing for Single Stuck Faults Test Compression Built-In Self-Test Design for Testability (II)

t l Critical Path Tracing A line l has a critical value v in the test (vector) t iff t detects the fault l s-a-!v. A line with a critical value in t is said to be critical in t. POs are critical and the others are found by backtracing. Paths composed of critical lines are critical paths. A gate input is sensitive (in a test t) if complementing its value changes the value of the gate output. If a gate output is critical, then its sensitive inputs, if any, are also critical. t D=1/0 l

Example 1 E J B A C D Hi Hj F H I G K Gi Gj Ci Cj 1

Self-Masking Stem B is self-masking. Stem B is critial. 1 A B C Bi Bj Z Stem B is self-masking. 1 A B C Bi Bj E F G Z Stem B is critial.

Capture Line Let t be a test that activates fault f in a single-output combinational circuit. Let y be a line with level ly, sensitized to f by t. If every path sensitized to f either goes through y or does not reach any line with level greater than ly, then y is said to be a capture line of f in test t. A capture is a bottleneck for the propagation of fault effects. A test t detects the fault f iff all the capture lines of f in t are critical in t.

Cones & Fanout-Free Region A Cone contains all the logic feeding one primary output. To take advantage of the simplicity of critical path tracing in fanout-free circuits, within each cone we identify fanout-free regions (FFRs). The inputs of a FFR are checkpoints of the circuit, namely fanout branches and primary inputs. The output of a FFR is either a stem or a primary output. J B A C D Hi Hj F I G H Gi Gj Ci Cj

A Typical Combinational Circuit Testability Controllability Observability A Typical Combinational Circuit

STAFAN: Statistical Fault Analysis Agrawal, 1985 Vector-based probability C1(l): The probability causing the output of line l a value v O(l): The probability propagating response from l to any output. Example: x y z w

Syllabus & Chapter Precedence Introduction Modeling Logic Simulation Fault Modeling Fault Simulation Testing for Single Stuck Faults Test Compression Built-In Self-Test Design for Testability (I)

Testing for Single Stuck Faults Test Generation: Random vs. Diterministic ATPG for SSFs in Combinational Circuits ATPG for SSFs in Sequential Circuits

Test Generation: Random vs. Deterministic Fault Selection Test Generation Fault Simulation Fault Dropping TE enough? Done No Test Selection Fault Simulation Fault Dropping TE enough? Done No

Test Generation: Random vs. Deterministic #patterns Test Efficiency Test set generation time Expected time per pattern

5-Value Operations v/vf 0/0 1/1 1 1/0 D ↓ 0/1 ↑ AND Notations 1 D X OR 1 D X Notations v/vf 0/0 1/1 1 1/0 D ↓ 0/1 ↑ OR 1 D X

Test Generation for Fanout-Free Tree 1. Set all values to X Justify for Enabling X X X X X X X 2. Justify(l, ~v) 3. Propagate(l, v/vf ) X X X X X X X

Decision Process in Justification State 1 1 State 2 1

Decision Process in Justification State 1 000 001 010 011 100 101 110 Branches of Decision Tree

Backtracking in Decision Tree Sub- Process Conflict or Contradiction In typical circuits, test generation for some faults usually have more than thousands of backtracking

Test Generation for Fanout-Free Tree Possible Backtracking with Fanout 1. Set all values to X Justify for Enabling X X If Conflict? X Backtracking X X X X 2. Justify(l, ~v) 3. Propagate(l, v/vf ) X X X X X X X

Concept of Frontiers J-Frontier D-Frontier all gates keeping track of unsolved D-frontier: all gates with any D or \D on their inputs – a queue waiting for propagation. J-Frontier D-Frontier

Bonus Project 1 Write a set of C (or C++) programs to read the ISCAS85 benchmark. Construct an internal model (data structure). Do functional logic simulation in the internal model. Add a bit for fault insertion in each gate and do serial fault simulation.

Bonus Project 2 Be familiar with a test tool in this laboratory environment, say, SynTest, Mentor or Synopsys, e.t.c. Try at least 3 instances in ISCAS89 benchmark, do the full-scan test syntheses and obtain the test patterns and report the associated parameters (i.e., fault coverage, test efficiency and approximated area overhead.)