Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 30: November 12, 2014 Memory Core: Part 2

Today Multiport SRAM DRAM Penn ESE370 Fall DeHon 2

Memory Bank Penn ESE370 Fall DeHon 3

Multiport RAM Penn ESE370 Fall DeHon 4

Mulitport Perform multiple operations simultaneously –E.g. Processor register file add r1,r2,r3 R3  R1+R2 Requires two reads and one write Penn ESE370 Fall DeHon 5

Simple Idea Add access transistors to 5T Penn ESE370 Fall DeHon 6

Watch? What do we need to be careful about? Penn ESE370 Fall DeHon 7

Adding Write Port Penn ESE370 Fall DeHon 8

Write Port What options does this raise? Penn ESE370 Fall DeHon 9

Opportunity Asymmetric cell size Separate sizing constraints –Weak drive into write port (W restore ) –Strong drive into read port (W buf ) Penn ESE370 Fall DeHon 10

Multiple Read Ports What if want more than two read ports? Can we do this again? Penn ESE370 Fall DeHon 11

Robust Read What makes more robust? Sizing impact? Penn ESE370 Fall DeHon 12

Isolate BL form Mem How make this work? Sizing impact? Penn ESE370 Fall DeHon 13

Isolate BL form Mem Penn ESE370 Fall DeHon 14 Larger, but more robust Essential for large # of read ports Precharge ReadData High

Multiple Write Ports How about multiple write ports? –Assuming at most one write per word Penn ESE370 Fall DeHon 15

Multiple Write Ports Penn ESE370 Fall DeHon 16

DRAM Penn ESE370 Fall DeHon 17

Penn ESE370 Fall DeHon 18 Some Numbers (memory) Register as stand-alone element (14T)  4K 2 Static RAM cell (6T)  1K 2 –SRAM Memory (single ported) Dynamic RAM cell (DRAM process)  Dynamic RAM cell (SRAM process)  300 2

1T 1C DRAM Simplest case – Memory is capacitor –Feature of DRAM process is ability to make large capacitor compactly Penn ESE370 Fall DeHon 19

DRAM Capacitors Sunami, Solid State Circuit, January 2008 Penn ESE370 Fall DeHon 20

DRAM Trench Capacitor Sunami, Solid State Circuit, January 2008 Penn ESE370 Fall DeHon 21

DRAM Capacitance Scaling Sunami, Solid State Circuit, January 2008 Penn ESE370 Fall DeHon 22

1T DRAM What happens when read this cell? Penn ESE370 Fall DeHon 23 Cbit << Cbl

1T DRAM On read, charge sharing –V BL = (C bit /C BL )V store Small swing on bit line –Must be able to detect –Means want large C bit limit bits/bitline so V BL large enough Cell always depleted on read –Must be rewritten Penn ESE370 Fall DeHon 24

Penn ESE370 Fall DeHon 25 Dynamic RAM Takes sharing idea one step further Share refresh/restoration logic as well Only left with access transistor and capacitor

3T DRAM Penn ESE370 Fall DeHon 26

3T DRAM How does this work? –Write? –Read? Penn ESE370 Fall DeHon 27

3T DRAM Correct operation not sensitive to sizing Does not deplete cell on read No charge sharing with stored state All NMOS (single well) Precharge ReadData Must use V dd +V TN on W to write full voltage Penn ESE370 Fall DeHon 28

Energy (if time permits) Penn ESE370 Fall DeHon 29

Single Port Memory What fraction is involved in a read/write? What are most cells doing on a cycle? Reads are slow –Cycles long  lots of time to leak Penn ESE370 Fall DeHon 30

ITRS nm Penn ESE370 Fall DeHon 31 High Performance Low Power I sd,leak 100nA/  m50pA/  m I sd,sat 1200  A/  m560  A/  m C g,total 1fF/  m0.91fF/  m V th 285mV585mV C 0 =  m × C g,total

High Power Process V=1V d=1000  =0.5 W access =W buf =2 Full swing for simplicity C sc = 0 –(just for simplicity, typically <C load ) BL: C load =1000C 0 ≈ 45 fF = 45× F W N = 2  I leak = 9×10 -9 A P= (45× ) freq ×9×10 -9 W Penn ESE370 Fall DeHon 32

Relative Power P= (45× ) freq ×9×10 -9 W P= (4.5× ) freq + 9×10 -6 W Crossover freq<200MHz How partial swing on bit line change?  Reduce dynamic energy  Increase percentage in leakage energy  Reduce crossover frequency Penn ESE370 Fall DeHon 33

Consequence Leakage energy can dominate in large memories Care about low operating (or stand-by) power Use process or transistors with high V th –Reduce leakage at expense of speed Penn ESE370 Fall DeHon 34

Idea Memory can be compact Rich design space Demands careful sizing Penn ESE370 Fall DeHon 35

Admin Project 2 out –Milestone due Tuesday Friday here for Memory Periphery Monday in Detkin Penn ESE370 Fall DeHon 36