Carbon Nanotube Technology An Alternative in Future SRAM memories UPC CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011

Introduction CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011 OBJECTIVE: to evaluate the variability in Carbon nanotube Field Effect Transistor (CNFET) as well as its real capability to be a promising alternative to Si-CMOS technology. 1.Impact of carbon nanotube (CNT) diameter variations and the presence of metallic CNTs in the transistor (device level). 2. Comparison between Si-CMOS and CNFET 6T SRAM cells (circuit level). In Si-bulk CMOS technology the variability of the device parameters is a key drawback and it may be a limiting factor for further miniaturizing nodes.

CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011 Carbon Nanotubes (CNTs) Graphene Carbon nanotube Metallic Semiconducting DiameterBehaviour Rest of Chiral vector angle of the atom arrangement along the tube Device level

CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011 Carbon Nanotube Field Effect Transistors (CNFETs) An “Ideal” MOSFET-like CNFET is formed by 1 or more semiconducting CNTs perfectly aligned and well-positioned whose section under the gate is intrinsic and the s/d extension regions are n/p doped. Promising candidates to replace silicon CMOS due to its high performance There are some imperfections inherent to CNT synthesis and CNFET manufacturing process that may eclipse the expectations Device level

SOURCES OF VARIATION CNT growth process CNFET manufacturing process Percentage of m-CNTs Diameter variations S/D doping variations Mispositioned and misaligned CNTs NO control of chirality CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011 Metallic CNTs Semiconducting CNTs Device level

CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011 CNFET device model [1] [1] J. Deng and H.-S. Wong, “A compact spice model for carbon-nanotube field-effect transistors including nonidealities and its application part II: Full device model and circuit performance benchmarking,” Electron Devices, IEEE Transactions on, vol. 54, no. 12, pp. 3195–3205, Device level

CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011 Monte Carlo experiment Example of I DS − V DS distribution for 50 CNFET samples. Device level

CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011 STD (σ) of V TH and K Percentage of variation (100x3σ/μ) Device level

CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011 Variability analysis and performance in CMOS and CNFET SRAM 6T cells Circuit level

CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011 Circuit level CNFET SRAM cell versus Si-MOSFET SRAM cell (nominal comparison)

CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011 Circuit level CNFET SRAM cell versus Si-MOSFET SRAM cell (variability comparison)

CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011 Circuit level CNFET SRAM cell versus Si-MOSFET SRAM cell (variability comparison)

CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011 Circuit level CNFET SRAM cell versus Si-MOSFET SRAM cell (variability comparison)

CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011 Device level Conclusions CNFETs are promising candidates to replace Si-MOSFETs due to their high current driving capability, tolerance to temperature and low leakage currents. Manufacturing variability, that is one of the key limiting factors in silicon-MOS technology, has been investigated for such CNFET devices. Considering a range of metallic tubes from 33% (current growth methods) to 0% (perfection) and a realistic distribution of diameters, it has been shown that the variability of both K factor and V TH is lower than CMOS for transistors with just 8 nanotubes, and much better for 12 tubes. In a future scenario with a narrower distribution of CNT diameters, variation for both parameters could reach levels from 15% to 25%, fact that would allow a design procedure without the stress caused by variability in current conventional technology.

CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011 Circuit level Conclusions CNFETs can be also considered as a potential alternative to CMOS in memory systems. CNT technology presents better performance than CMOS technologies. However the implementation maturity of CNFET is still pending of several years of development. Variability analysis shows as a promising prospect, that even for todays CNFETs performance, its variability is comparable with that of Si-MOS technology in a scenario which we have called ”moderated”. Therefore, improvements in the control of chirality, the variability of CNFETs could be lower than in that moderated scenario.

Thanks for your attention! CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011

Carbon Nanotubes (CNTs) Graphene Carbon nanotube Diameter & V TH Device level

CASTNESS’11 WORKSHOP ON TERACOMP FET Projects, Rome, January 17 th -18 th 2011 Mean (μ) of V TH and K Mean of V th as T m Mean of V th as N Mean of K as T m Mean of K as N Device level