5/31/07IWLS 20071 Computing Beyond CMOS Intense research into novel materials and devices: Carbon Nanotubes… Molecular Switches… Biological Processes…

Slides:



Advertisements
Similar presentations
NanoFabric Chang Seok Bae. nanoFabric nanoFabric : an array of connect nanoBlocks nanoBlock : logic block that can be progammed to implement Boolean function.
Advertisements

5.5 Encoders A encoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes.
Digital Logic Design Week 7 Encoders, Decoders, Multiplexers, Demuxes.
Combinational Circuits
Multiplexer. A multiplexer (MUX) is a device which selects one of many inputs to a single output. The selection is done by using an input address. Hence,
ELE 523E COMPUTATIONAL NANOELECTRONICS W7-W8: Probabilistic Computing, 20/10/ /10/2014 FALL 2014 Mustafa Altun Electronics & Communication Engineering.
Weikang Qian Ph.D. Candidate Electrical & Computer Engineering
Marc Riedel Synthesizing Stochasticity in Biochemical Systems Electrical & Computer Engineering Jehoshua (Shuki) Bruck Caltech joint work with Brian Fett.
Module Locking in Biochemical Synthesis Brian Fett and Marc D. Riedel Electrical and Computer Engineering University of Minnesota Brian’s Automated Modular.
CMOL: Device, Circuits, and Architectures Konstantin K.Likharev and Dmitri B. Strukov Stony Brook University 697GG Nano Computering Fall 2005 Prepared.
1 CSE 591-S04 (lect 14) Interconnection Networks (notes by Ken Ryu of Arizona State) l Measure –How quickly it can deliver how much of what’s needed to.
Xin Li, Weikang Qian, Marc Riedel, Kia Bazargan & David Lilja A Reconfigurable Stochastic Architecture for Highly Reliable Computing Electrical & Computer.
Proof: Synthesize cubes so that cube c k has n − i k literals and cubes c k and c l are disjoint, for any 0 ≤ k < l ≤ λ − 1. Weikang Qian and Marc D. Riedel.
Marc Riedel The Synthesis of Stochastic Logic for Nanoscale Computation IWLS 2007, San Diego May 31, 2007 Weikang Qian and John Backes Circuits & Biology.
Address Generation for Nanowire Decoders Jia Wang, Ming-Yang Kao, Hai Zhou Electrical Engineering & Computer Science Northwestern University U.S.A.
Gene Regulatory Networks - the Boolean Approach Andrey Zhdanov Based on the papers by Tatsuya Akutsu et al and others.
Array-Based Architecture for FET-Based, Nanoscale Electronics André DeHon 2003 Presented By Mahmoud Ben Naser.
1 Jianwei Dai, Lei Wang, and Faquir Jain Department of Electrical and Computer Engineering University of Connecticut Analysis of Defect Tolerance in Molecular.
Weikang Qian The Synthesis of Stochastic Logic to Perform Multivariate Polynomial Arithmetic Abstract Ph.D. Student, University of Minnesota Marc D. Riedel.
Boolean Algebra and Truth Table The mathematics associated with binary number system (or logic) is call Boolean: –“0” and “1”, or “False” and “True” –Calculation.
Circuit Engineers Doing Biology Marc D. Riedel Assistant Professor, Electrical and Computer Engineering University of Minnesota Café Scientifique A Discourse.
1 CSE 20: Lecture 7 Boolean Algebra CK Cheng 4/21/2011.
Emerging Logic Devices
©2004 Brooks/Cole FIGURES FOR CHAPTER 18 CIRCUITS FOR ARITHMETIC OPERATIONS Click the mouse to move to the next page. Use the ESC key to exit this chapter.
Shannon’s Expansion Muxes and Encoders. Tri-State Buffers  A tri-state buffer has one input x, one output f and one control line e Z means high impedance,
1 Stochastic Logic Beyond CMOS... Prof. Mingjie Lin.
Nanoscale Digital Computation Through Percolation Mustafa Altun Electrical and Computer Engineering DAC, “Wild and Crazy Ideas” Session ─ San Francisco,
10-1 Chapter 10 - Advanced Computer Architecture Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring.
1 Introduction to Abstract Mathematics Applications : Digital Logic Circuits 2.4 and Number Systems 2.5 Instructor: Hayk Melikya
Ketan Patel, Igor Markov, John Hayes {knpatel, imarkov, University of Michigan Abstract Circuit reliability is an increasingly important.
Building Cad Prototyping Tool for Emerging Nanoscale Fabrics Catherine Dezan Joined work between Lester( France.
Digital Logic Problems (II) Prof. Sin-Min Lee Department of Mathematics and Computer Science.
1 Combinational Logic Design Digital Computer Logic Kashif Bashir
Computer Science and Engineering Parallel and Distributed Processing CSE 8380 January Session 4.
EE5393, Circuits, Computation, and Biology Computing with Probabilities 1,1,0,0,0,0,1,0 1,1,0,1,0,1,1,1 1,1,0,0,1,0,1,0 a = 6/8 c = 3/8 b = 4/8.
A Reconfigurable Low-power High-Performance Matrix Multiplier Architecture With Borrow Parallel Counters Counters : Rong Lin SUNY at Geneseo
June 2005Computer Architecture, Background and MotivationSlide 1 Part I Background and Motivation.
DAT2343 Arithmetic Circuits For Unsigned Binary Values © Alan T. Pinck / Algonquin College; 2003.
Computing with Defects
Marc Riedel – EE5393 The Synthesis of Robust Polynomial Arithmetic with Stochastic Logic Electrical & Computer Engineering University of Minnesota.
Multi-state System (MSS) Basic Concepts MSS is able to perform its task with partial performance “all or nothing” type of failure criterion cannot be.
Joint Power and Channel Minimization in Topology Control: A Cognitive Network Approach J ORGE M ORI A LEXANDER Y AKOBOVICH M ICHAEL S AHAI L EV F AYNSHTEYN.
ELE 523E COMPUTATIONAL NANOELECTRONICS W8-W9: Probabilistic Computing, 2/11/ /11/2015 FALL 2015 Mustafa Altun Electronics & Communication Engineering.
DO LOCAL MODIFICATION RULES ALLOW EFFICIENT LEARNING ABOUT DISTRIBUTED REPRESENTATIONS ? A. R. Gardner-Medwin THE PRINCIPLE OF LOCAL COMPUTABILITY Neural.
ELE 523E COMPUTATIONAL NANOELECTRONICS W10: Defects and Reliability, 16/11/2015 FALL 2015 Mustafa Altun Electronics & Communication Engineering Istanbul.
Marc Riedel Associate Professor, Electrical and Computer Engineering University of Minnesota ITA – Feb. 14, 2014 (“Singles’ Awareness Day”) Probability.
ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Third Edition, by Allan R. Hambley, ©2005 Pearson Education, Inc. Chapter 7 Logic Circuits.
Minute Paper 4/4/04 Z=50+j86.7=100
Bacteria are engineered to produce an anti-cancer drug: Design Scenario drug triggering compound E. Coli.
EE5393, Circuits, Computation, and Biology Computing with Probabilities 1,1,0,0,0,0,1,0 1,1,0,1,0,1,1,1 1,1,0,0,1,0,1,0 a = 6/8 c = 3/8 b = 4/8.
COMPUTER ORGANISATION.. LAB. تنظيم الحاسبات.. عملي
Bacteria are engineered to produce an anti-cancer drug: Design Scenario drug triggering compound E. Coli.
Chapter 12. Chapter Summary Boolean Functions Representing Boolean Functions Logic Gates Minimization of Circuits (not currently included in overheads)
Everything is a number Everything in a computer memory and on storages is a number. Number  Number Characters  Number by ASCII code Sounds  Number.
A Deterministic Approach to Stochastic Computation
Digital Design Jeff Kautzer Univ Wis Milw.
VLSI Presentation 4 – Bit Shifter
Maxwell-Boltzmann velocity distribution
Emerging Logic Devices
Biological Processes…
Maxwell-Boltzmann velocity distribution
  State Encoding مرتضي صاحب الزماني.
The Building Blocks: Binary Numbers, Boolean Logic, and Gates
Part I Background and Motivation
XOR Function Logic Symbol  Description  Truth Table 
ELE 523E COMPUTATIONAL NANOELECTRONICS
Half & Full Subtractor Half Subtractor Full Subtractor.
Half & Full Subtractor Half Subtractor Full Subtractor.
♪ Embedded System Design: Synthesizing Music Using Programmable Logic
Presentation transcript:

5/31/07IWLS Computing Beyond CMOS Intense research into novel materials and devices: Carbon Nanotubes… Molecular Switches… Biological Processes…

5/31/07IWLS Computing Beyond CMOS Many technologies still in exploratory phase: ! 

5/31/07IWLS Nanoscale Circuits Topological constraints. Inherent randomness. High defect rates. Features: Challenges: High density of bits. Identify general traits that impinge upon logic synthesis: carbon nanowire crossbar

Circuit Modeling logic Characterize probability of outcomes. inputsoutputs Model defects, variations, uncertainty, etc.:

Circuit Modeling logic Functional description is Boolean: inputsoutputs

Consider a probabilistic interpretation: logic stochastic logic inputsoutputs Circuit Modeling

stochastic logic Stochastic Logic inputsoutputs ,1,1,0,1,0,1,1,0,1,… 1,0,0,0,1,0,0,0,0,0,… p 1 = Prob(one) p 2 = Prob(one) serial bit streams Consider a probabilistic interpretation:

stochastic logic Stochastic Logic inputsoutputs Consider a probabilistic interpretation:

stochastic logic Stochastic Logic p 1 = Prob(one) p 2 = Prob(one) parallel bit streams Consider a probabilistic interpretation:

stochastic logic Stochastic Logic parallel bit streams Consider a probabilistic interpretation:

stochastic logic Stochastic Logic Interpret outputs according to fractional weighting: 0 1 0

5/31/07IWLS Synthesis of Stochastic Logic Circuit that computes a probability distribution corresponding to a logical specification. Given a technology characterized by: Synthesize: High degree of structural parallelism. Inherent randomness in logic/interconnects. Cast problem in terms of arithmetic operations. Perform synthesis with binary moment diagrams. Strategy:

5/31/07IWLS A real value x in [ 0, 1 ] is encoded as a stream of bits X. For each bit, the probability that it is one is: P( X=1 ) = x. Probabilistic Bundles x X

5/31/07IWLS Arithmetic Operations Multiplication(Scaled) Addition ba BPAP CPc    )()( )( ) )1( ()](1[)()( )( bsas BPSPAPSP CPc   

5/31/07IWLS Nanowire Crossbar (idealized)

5/31/07IWLS Nanowire Crossbar (idealized) Randomized connections, yet nearly one-to-one.

5/31/0717 Shuffled AND

5/31/07IWLS Takes the AND of randomly chosen pairs. Multiplication Shuffled AND

5/31/0719 Bundleplexing

Scaled Addition Randomly selection of wires from different bundles,. Randomly selection of wires from different bundles, according to a fixed ratio. ¾ Bundleplexer

5/31/07IWLS Stochastic Logic Shuffled ANDs, Bundleplexers { { A 0 A 1... { A n } B

5/31/07IWLS Stochastic Logic Shuffled ANDs, Bundleplexers { { { }