1 Workshop Topics - Outline Workshop 1 - Introduction Workshop 2 - module instantiation Workshop 3 - Lexical conventions Workshop 4 - Value Logic System Workshop 5 - Data types A Workshop 6 - Data types B Workshop 7 - Operators Workshop 8 - Signed arithmetic Workshop 9 - Behavioral modeling A Workshop 10 - Behavioral modeling B Workshop 11 - Behavioral modeling C Workshop 12 - Data flow modeling Workshop 13 - Coding Styles

2 Lexical conventions The basic lexical conventions used by Verilog HDL are similar to those in the C programming language. Verilog HDL is a case-sensitive language. All keywords are in lowercase. White space characters are: Blank spaces, Tabs, New-line Statement Terminator: Verilog models consist of a list of statements declaring relationships between a model and its environment, and between signals within a model. Statements are terminated by a semicolon( ; ) module full_addr (A, B, Cin, S, Cout) ; input A, B, Cin ; output wire S, Cout ; assign {Cout, S} = A + B + Cin ; // Concatenation endmodule

3 Identifiers Identifiers are names given to an object, such as a register or a function or a module, so that it can be referenced from other places in a description Identifiers must begin with an alphabetic character or the underscore character (a-z A-Z _ ) Identifiers may contain alphabetic characters, numeric characters, underscore, and dollar sign (a-z A-Z 0-9 _ $ ) Identifiers can be up to 1024 characters long Identifier cannot start with a number or dollar sign ($) Escaped Identifiers begin with backslash (\) and end with white space (space, tab or new line)

4 Identifiers cont., Comments All characters within the Escape Identifier, are processed literally. Any printable ASCII character can be included. Identifiers examples: wire a1 ; // wire is a keyword, a1 is an identifier reg sum ; // reg is a keyword, sum is an identifier Escaped Identifier examples: \a+b-c \**my_name** Comments: There are two forms to introduce comments. Single line comments begin with “// “ and end with a carriage return. // This is a one line comment Multi Line comments begin with the “/*” and end with “*/” /* This is a multiple lines comments */

5 Integer Numbers Verilog HDL allows integer numbers to be specified as: Sized or Unsized numbers ( Unsized size is 32 bits ) In a radix of binary, octal, decimal, or hexadecimal Radix and hex digits (a, b, c, d, e, f) are case insensitive Spaces are allowed between the size, radix and value Syntax: ' size in bits, radix in b, d, o, h

6 Number Representation 549 // unsized decimal number ‘h 8FF // unsized hex number ‘o765 // unsized octal number 4 ’b11 // 4-bit binary number ’b10x // 3-bit binary number with LSB unknown 5 ’d3 // 5-bit decimal number -4 ’b11 // 4-bit two’s complement of 0011 = 1101 = 4’hd

7 Integer Numbers - Examples Unsized Numbers: 792 // a decimal number 8d9 // Illegal, hexadecimal must be specified with ‘h ‘h 7d9 // an unsized hexadecimal number d9 ‘o 7746 // an unsized octal number // stored as Sized Numbers: 12 ‘h x // a 12 bit unknown number 10 ‘d 17 // a 10 bit constant with the value 17 4‘b 110z // a 4 bit binary number with LSB in Hi-Z state 8’hAA // stored as

8 Integer Numbers (2) If size is ommitted:  It is inferred from the value or  It takes the simulation specific number of bits or  It takes the machine specific number of bits (32/64b) If radix is ommitted too, decimal is assumed  15 = ’d 15

9 Integer Numbers (3) One can insert “_” to improve readability, 12 ’b 000_111_010_ ’b ’o 07_24 “?” question mark – substitutes z in numbers for better readability: 8 `b111? // == 8 `b111Z Zero fill / bit extension: If a numeric value does not contain enough digits to fill the specified number of bits, the high order bits are filled with zeros. If the specified MSB is an x or z, the x/z is left extended to fill the bit field. 16 ’h39  16 ’h0039  16 ’b ’hz  8 ’hzz  16 ’bzzzz zzzz

10 Signed and Unsigned Numbers Verilog Supports both types of numbers, but with certain restrictions. Any number that does not have negative sign prefix is a positive number. Or indirect way would be "Unsigned" Negative numbers can be specified by putting a minus sign (-) before the size for a constant number, thus become signed numbers. Verilog internally represents negative numbers in 2's compliment format.

11 Signed and Unsigned Numbers Examples Negative numbers (- sign before the size) are represented in 2's complement form. Any number without a – sign is an unsigned number -4’d7 // stored as sd3 // used for performing signed integer math 4’d-2 // Illegal specification -5’ha // stored as ’b101 // stored as 1011 wire signed [N-1:0] din ; // a net that holds a signed value reg signed [M-1:0] dout ; /* a variable that holds a signed value */

12 Real Numbers Verilog supports real constants and variables Real Numbers can not contain 'Z' and 'X' Real numbers may be specified in either decimal or scientific notation: .  E Verilog converts real numbers to integers by rounding. Real numbers are rounded off to the nearest integer when assigning to integer. Examples:Real NumberDecimal Number E

13 String A sequence of characters enclosed in double quotes. Must be contained in a single line (w/o carriage return). String is treated as a sequence of one-byte ASCII values. Example: “Verilog HDL Concepts” Verilog strings are implemented with regs. The reg holds the ASCII values of each character of the string. reg [8*12:0] string_val ; // can hold up to 13 chars string_val = “Hello Verilog”; string_val = “hello”; // MS Bytes are filled with 0 string_val = “I am overflowed”; // “I ” is truncated Accept C-like escape characters: \n = newline, \t = tab, \b = backslash, \” = quote mark (“), % = % sign