Apu, IDe, MobileMAN meeting, HelsinkiPage 1/18 MobileMAN Hardware development for the MAC module current state and outlook IAB meeting By Ralph Bernasconi, Ivan Defilippis, Silvia Giordano, Alessandro Puiatti SUPSI Manno Helsinki, June

Apu, IDe, MobileMAN meeting, Helsinki Page 2/18 Contents Introduction Completed work Current work Next steps Data structure description Questions?

Apu, IDe, MobileMAN meeting, Helsinki Page 3/18 Introduction Project’s SUPSI-DIE goals (reminder) Provide flexible development- and test-bed for enhanced WLAN protocol (CNR) Bursty responsive MAC Better contention scheme (backoff); avoid collisions even for dense and active networks Ensure compatibility with x Provide few samples to partners Provide inputs for new standard

Apu, IDe, MobileMAN meeting, Helsinki Page 4/18 Analysis of the Market for the implementations Available solutions? Which solution best suits our needs? Criteria are: - Cost - Reliability - Flexibility - Access to the software code - Access to the firmware - Easy development environment - Secure and prompt technical support Completed work ( 1/8)

Apu, IDe, MobileMAN meeting, Helsinki Page 5/18 Alternatives for development: Start from scratch: - Implementation of a complete chain: MAC - BB - RF Start “in the middle”: - Implementation of the MAC only Start from an already implemented solution: - Change software and firmware for our purpose Completed work (2/8)

Apu, IDe, MobileMAN meeting, Helsinki Page 6/18 Selected solution Start “in the middle” BB and RF already developed by Elektrobit AG: -DT20 Modem (Intersil Prism-I chipset) Implement MAC on a DSP microcontroller - TI C6713 board (Texas Instruments) Completed work (3/8)

Apu, IDe, MobileMAN meeting, Helsinki Page 7/18 Level-Switch interfaces DT20 - Modems TI C6713 boards JTAG interface Development system Completed work (4/8)

Apu, IDe, MobileMAN meeting, Helsinki Page 8/18 Completed work (5/8)

Apu, IDe, MobileMAN meeting, Helsinki Page 9/18 Deep analysis of the standard Procedures and flowchart for the Tx/Rx further implementation Implementation on the DSP board CRC on FPGA Tx/Rx between MAC and BB Channel Sensing mechanism on MAC (MAC – RF) MAC Tx mechanism MAC Rx mechanism Completed work (6/8)

Apu, IDe, MobileMAN meeting, Helsinki Page 10/18 Implementations on the DSP board (cont.) Standard backoff mechanism Regular frame generation Fragmented frame generation RTS/CTS/DATA/AK handshake MAC Address recognition Channel contention Completed work (7/8)

Apu, IDe, MobileMAN meeting, Helsinki Page 11/18 Tests done (2 systems/boards) Stress tests in Tx between boards connected by cable Stress tests in Rx between boards connected by cable Stress tests in Tx/Rx between boards connected by cable Stress tests in Tx/Rx between boards in wireless mode - Standard backoff tested successfully - Fragmented Tx/Rx tested successfully - RTS/CTS/DATA/AK handshake tested successfully Completed work (8/8)

Apu, IDe, MobileMAN meeting, Helsinki Page 12/18 Assembly of the 3rd system/board Definition of the host interface mechanism (via IEEE-1394/FireWire) Definition of the standard packets data-structure Definition of data-structure extensions for cross- layering implementation Current work

Apu, IDe, MobileMAN meeting, Helsinki Page 13/18 Implementation on the DSP NAV (Network Allocation Vector) Test of a 3 nodes network (with above functionality) Implementation and test of the host interface mechanism Implementation and test of the standard packets data-structure Implementation and test of data-structure extensions for cross- layering Implementation and test of the modified (CNR-Pisa) backoff mechanism Next steps

Apu, IDe, MobileMAN meeting, Helsinki Page 14/18 Memory slotted in parameterized slot length (default frame max length) Descriptor mechanism for handling data Different queues for managing data transfer: From MAC to PHY and from PHY to MAC From MAC to Host and from Host to MAC Implementation of priority mechanisms for each queue Control flags in descriptor in which: DATA = Frame DATA = parameters for/from cross-layering Data Structure description (1/4)

Apu, IDe, MobileMAN meeting, Helsinki Page 15/18 MAC header x FCS x Frame Memory Data Area MAC (DSP) Frame body x+1 Frame body x Descriptor x Descriptor x+1 End HMQ Descriptor x+n+1 MAC h. y+n-1 Frame body y+n-1 FCS y+n-1 MAC h. y+n Frame body y+n FCS y+n Descriptor x+n Frame body x+n Frame body x+n+1 Descriptor y+n-1 Descriptor y+n End MPQ MAC to PHY Queue Begin Host to MAC Queue Begin Host to MAC Queue End MPQ End HMQ MAC h. y+n+1 FCS y+n+1 Frame body y+n+1 Descriptor y+n+1 Data Structure description (2/4)

Apu, IDe, MobileMAN meeting, Helsinki Page 16/18 MAC header y FCS y Frame Memory Data Area MAC (DSP) Frame body x+1 Frame body x Descriptor x Descriptor x+1 End MHQ MAC h. y+1 Frame body y+1 FCS y+1 MAC h. y+2 Frame body y+2 FCS y+2 Descriptor x+n Frame body y Descriptor y+2 Descriptor y+1 End PMQ PHY to MAC Queue Begin MAC to Host Queue Begin Descriptor y Frame body x+n End MHQ PHY to MAC Queue Begi n Frame body x+n+1 Descriptor x+n+1 Data Structure description (3/4)

Apu, IDe, MobileMAN meeting, Helsinki Page 17/18 Management of queues with different levels of priority Descriptor 1 Pn Descriptor 1 Pn-1 End Q Descriptor P0 Descriptor 2 Pn Descriptor 3 Pn Descriptor 4 Pn Descriptor k Pn End Q-Pn Descriptor 2 Pn-1 Descriptor h Pn-1 End Q-Pn-1 Descriptor 2 P0 Descriptor 3 P0 Descriptor g P0 End Q-P0 Data Structure description (4/4)

Apu, IDe, MobileMAN meeting, Helsinki Page 18/18 Questions? Thanks for your attention!