By Premananda B.S. premanandabs@gmail.com Design of VLSI Systems By Premananda B.S. premanandabs@gmail.com

Modules Design Economics Special-purpose Subsystems Testing and Verification

Design Economics

Design Economics IC designer should able to predict the cost and the time to design a particular IC. This guides the choice of implementation strategy. Selling price Stotal = Ctotal / (1-m) Where m = profit margin and Ctotal = total cost Cost to produce an IC are divided into: Nonrecurring engineering costs (NRE) Recurring costs Fixed costs

Non-recurring Engineering Costs Cost once spent during the design of an IC, they include: Engineering design cost Prototype manufacturing cost i.e., Ftotal = Etotal + Ptotal NRE can be viewed as an investment for which there is a required rate of return. Engineering design costs, include: Personnel costs Support costs Prototype manufacturing costs, include: Mask cost Test fixture costs Package tooling

The personnel cost include labor for: Architectural design Logic capture Simulation for functionality Layout of modules and chip Timing verification DRC and tapeout procedures Test generation The support costs are: Computer costs CAD software costs Training

Recurring Costs The cost that recurs every time an IC is sold. The total cost is Ct = Cprocess + Cpack + Ctest Cprocess = W / (N.Yd.Ypack.) Fabrication Wafer cost / (Dice per wafer * Yield) Wafer cost: $500 - $3000 Dice per wafer: Yield: Y = e-AD For small A, Y  1, cost proportional to area For large A, Y  0, cost increases exponentially Packaging Test

Fixed Costs Data sheets and application notes Marketing and advertising

Schedule Estimate the design cost and design time for the system. Selecting the strategy by which the ICs will be available in the right time and price. Experienced person. To estimate schedule some idea of the amount effort required to complete the design. Schedule is a function of personpower. Methods for improving the schedules: Using a high productivity design method Improving the productivity of a given technique Decreasing the complexity of the design task by partitioning

Personpower Tasks required are: Architectural design HDL capture Functional verification PAR Timing verification, signal integrity, reliability verification DRC and tapeout procedures Test generation

Example You want to start a company to build a wireless communications chip. How much venture capital must you raise? Because you are smarter than everyone else, you can get away with a small team in just two years: Seven digital designers Three analog designers Five support personnel

Solution Digital designers: Analog designers Support staff Fabrication salary overhead computer CAD tools Total: Analog designers Support staff salary overhead computer Total: Fabrication Back-end tools: Masks: Summary

Digital designers: Analog designers Support staff Fabrication Summary $70k salary $30k overhead $10k computer $10k CAD tools Total: $120k * 7 = $840k Analog designers $100k salary $100k CAD tools Total: $240k * 3 = $720k Support staff $45k salary $20k overhead $5k computer Total: $70k * 5 = $350k Fabrication Back-end tools: $1M Masks: $1M Total: $2M / year Summary 2 years @ $3.91M / year $8M design & prototype

Cost Breakdown New chip design is fairly capital-intensive Maybe you can do it for less?

Special-purpose Subsystems

Agenda Packaging Power Distribution I/O Clock Package options Chip-to-package connections Package parasitics Heat dissipation Power Distribution On-chip power distribution network Supply noise I/O Basic I/O pad circuits Clock Clock system architecture Global clock generation & distribution Local clock gaters

Packaging Package functions: Electrical connection of signals and power from chip to board, with little delay or distortion Mechanical connection of chip to board Removes heat produced on chip Protects chip from mechanical damage Compatible with thermal expansion Inexpensive to manufacture and test

Package Options Through-hole vs. surface mount

Multichip Modules Pentium Pro MCM Fast connection of CPU to cache Expensive, requires known good dice

Chip-to-Package Bonding Traditionally, chip is surrounded by pad frame: Metal pads on 100 – 200 mm pitch Gold bond wires attach pads to package Lead frame distributes signals in package Metal heat spreader helps with cooling

Advanced Packages Metal leads contribute parasitic inductance and coupling capacitors to their neighbors Fancy packages have many signal, power layers Like tiny printed circuit boards Flip-chip places connections across surface of die rather than around periphery Top level metal pads covered with solder balls Chip flips upside down Carefully aligned to package (done blind!) Heated to melt balls Introduces new testing problems

Package Parasitics Use many VDD, GND in parallel Inductance, IDD

Bond wires and lead frame contribute parasitic inductance to the signal traces. They also have mutual inductance and capacitive coupling to nearby signal traces, causing crosstalk when multiple signal switch. VDD & GND wires also have inductance from both bond wires and lead frame. They have nonzero resistance, which becomes important for chips drawing large supply current High performances packages often include bypass capacitors between VDD & GND.

Heat Dissipation 60 W light bulb has surface area of 120 cm2 Itanium 2 die dissipates 130 W over 4 cm2 Chips have enormous power densities Cooling is a serious challenge Advances in heat sinks, fans, packages have raised the practical limit for heat removal from about 8 W in 1985 to nearly 100 W today for affordable packaging. Package spreads heat to larger surface area Heat sinks may increase surface area further Fans increase airflow rate over surface area Liquid cooling used in extreme cases ($$$)

Thermal Resistance Temperature difference between transistor junctions and the ambient air is, DT = qjaP DT: temperature rise on chip qja: thermal resistance of chip junction to ambient P: power dissipation on chip Thermal resistances combine like resistors Series and parallel qja = qjp + qpa Series combination

Example Your chip has a heat sink with a thermal resistance to the package of 4.0° C/W. The resistance from chip to package is 1° C/W. The system box ambient temperature may reach 55° C. The chip temperature must not exceed 100° C. What is the maximum chip power dissipation? Solution is (100-55 C) / (4 + 1 C/W) = 9 W

Power Distribution Power Distribution Network functions: Carry current from pads to transistors on chip Maintain stable voltage with low noise Provide average and peak power demands Provide current return paths for signals Avoid electromigration & self-heating wearout Consume little chip area and wire Easy to lay out

Power Requirements VDD = VDDnominal – Vdroop Want Vdroop < +/- 10% of VDD L di/dt of bond wire and IR drop across on-chip wires are often a major source of supply noise Sources of Vdroop IR drops L di/dt noise IDD changes on many time scales

IR Drops: Ldi/dt Noise: Resistance of power supply network includes: resistance of the on-chip wires and vias, resistance of bond wires or solder bumps to the package, resistance of the package planes, resistance of the PCB planes IR drops arise from both average and instantaneous current requirements. Ldi/dt Noise: Inductance of power supply dominated by the inductance of the bond wires Modern packages devote many of their pins to power and ground to minimize supply inductance Two sources of current transients are switching I/O signals and changes between idle and active mode in the chip core

On-chip Bypass Capacitance The bypass capacitance is distributed across the chip so that a local spike in current can be supplied from nearby bypass capacitance rather than through the resistance of the overall power grid. power distribution network doesn’t really need to carry all of the peak current. Much of the difference between peak and average current may be supplied by local, on-chip bypass capacitors. On-chip bypass capacitors can reduce the amount of metal needed for distribution. It also greatly reduces the di/dt drawn from the package.

Symbiotic Bypass Capacitors Where are the bypass capacitors in this picture? Gates that are not switching at a given instant in time act as symbiotic bypass capacitors If only one gate in 60 switches at a given instant, the bypass capacitance is 30 times the switched capacitance

Power System Model Power comes from regulator on system board: Board and package add parasitic R and L Bypass capacitors help stabilize supply voltage But capacitors also have parasitic R and L Simulate system for time & frequency responses

Bypass Capacitors Need low supply impedance at all frequencies Ideal capacitors have impedance decreasing with w Real capacitors have parasitic R and L Leads to resonant frequency of capacitor

Frequency Response Use multiple capacitors in parallel Large capacitor near regulator has low impedance at low frequencies But also has a low self-resonant frequency Small capacitors near chip and on chip have low impedance at high frequencies Choose caps to get low impedance at all frequencies

Input / Output Input/Output System functions: Communicate between chip and external world Drive large capacitance off chip Operate at compatible voltage levels Provide adequate bandwidth Limit slew rates to control di/dt noise Protect chip against electrostatic discharge Use small number of pins (low cost)

I/O Pad Design Pad Types: VDD and GND Output Input Bidirectional Analog

VDD and GND Pads High-performance chips devote about half of their pins to power and ground. This large number of pins is required to carry the high current and to provide low supply inductance. Largest sources of noise in many chips is the ground bounce caused when the output pads switch. The pads must rapidly charge the large external capacitive loads, causing a big current spike and high Ldi/dt noise. The dirty power and ground lines serving the output pads are separated from the main power grid to reduce the coupling of I/O-related noise into the core.

Output Pads Drive large off-chip loads (2 – 50 pF) With suitable rise/fall times Requires chain of successively larger buffers Output transistors have gates longer than normal to prevent avalanche breakdown damage and over voltage is applied to the drains. Guard rings to protect against latchup Noise below GND injects charge into substrate Large nMOS output transistor p+ inner guard ring n+ outer guard ring In n-well

Input Pads Level conversion Higher or lower off-chip V May need thick oxide gates Noise filtering Schmitt trigger Hysteresis changes VIH, VIL Protection against electrostatic discharge

ESD Protection Static electricity builds up on your body Shock delivered to a chip can fry thin gates Must dissipate this energy in protection circuits before it reaches the gates ESD protection circuits Current limiting resistor Diode clamps ESD testing Human body model Views human as charged capacitor

Bidirectional Pads Need tristate driver on output: Use enable signal to set direction Optimized tristate avoids huge series transistors Improved tri-state buffer

Analog Pads Pass analog voltages directly in or out of chip: No buffering Protection circuits must not distort voltages

Clocking Synchronous systems use a clock to keep operations in sequence Distinguish this from previous or next Determine speed at which machine operates Clock must be distributed to all the sequencing elements Flip-flops and latches Also distribute clock to other elements Domino circuits and memories

Clock Distribution On a small chip, the clock distribution network is just a wire And possibly an inverter for clkb On practical chips, the RC delay of the wire resistance and gate load is very long Variations in this delay cause clock to get to different elements at different times This is called clock skew Most chips use repeaters to buffer the clock and equalize the delay Reduces but doesn’t eliminate skew

Example Skew comes from differences in gate and wire delay With right buffer sizing, clk1 and clk2 could ideally arrive at the same time. But power supply noise changes buffer delays clk2 and clk3 will always see RC skew

Review: Skew Impact Ideally full cycle is available for work Skew adds sequencing overhead Increases hold time too

Solutions Reduce clock skew Analyze clock skew Tolerate clock skew Careful clock distribution network design Plenty of metal wiring resources Analyze clock skew Only budget actual, not worst case skews Local vs. global skew budgets Tolerate clock skew Choose circuit structures insensitive to skew

Clock Skew Sources Clock Skew Sources are: systematic, random, drift, and jitter Note some engineers do not report jitter as part of the skew.

Clock System Architecture Synchronous chip interface with PLL

Phase-locked loop block diagram

Global Clock Distribution Networks Grids H-trees Spines Ad-hoc Hybrid

Clock Grids A clock grid is a mesh of horizontal and vertical wires driven from the middle or edges. Use grid on two or more levels to carry clock. Make wires wide to reduce RC delay. Ensures low skew between nearby points. But possibly large skew across die. Grids compensate for random skew. Grids consume a large amount of metal resources and hence a high switching capacitance and power consumption.

Alpha Clock Grids

H-Trees Fractal structure Delay variations cause skew Gets clock arbitrarily close to any point Matched delay along all paths Delay variations cause skew Buffers are added to serve as repeaters A and B might see big skew High random skew, drift and jitter between two nearby points

Itanium 2 H-Tree Four levels of buffering: Route around obstructions Primary driver Repeater Second-level clock buffer Gater Route around obstructions

Ad-hoc The clock is routed haphazardly with some attempt to equalize wire lengths or add buffers to equalize delay. Have low systematic skews because the buffer sizes can be adjusted until nominal delays are nearly equal. Subject to random skew.

Clock Spine If loads are uniform, the spine avoids the systematic skew of the grid by matching the length of the clock wires. Save power by not switching certain wires. System with many clocked elements may require a large number of serpentine routes, leading to high area and capacitance for the clock network. Clock spines have large skews between nearby elements driven by different serpentines.

Hybrid Networks Use H-tree to distribute clock to many points. Tie these points together with a grid. Hybrid combination of H-tree and grid offers lower skew. Hybrid approach has lower systematic skew, less susceptible to skew from non-uniform load distribution. Hybrid approach is regular, making layout of well-controlled transmission line structures easier. Ex: IBM Power4, PowerPC H-tree drives 16-64 sector buffers Buffers drive total of 1024 points All points shorted together with grid

Clock Generation

Local Clock Gaters Local Clock Gaters receives the global clock and produce the physical clocks required by clocked elements. Clock gaters are often used to stop or gate the clock to unused blocks of logic to save power. Different clock gaters are: Enabled or Gated clock Stretched clocks Nonoverlapping clocks Complementary clock Delayed, Pulsed clocks Clock Doubler Clock Buffer

Testing and Verification

Agenda Testing Fault Models Observability and Controllability Logic Verification Silicon Debug Manufacturing Test Fault Models Observability and Controllability Design for Test Scan BIST Boundary Scan

Testing Testing is one of the most expensive parts of chips Logic verification accounts for > 50% of design effort for many chips Debug time after fabrication has enormous opportunity cost Shipping defective parts can sink a company Example: Intel FDIV bug Logic error not caught until > 1M units shipped Recall cost $450M (!!!)

Main Difficulties in Testing Miniaturization Physical access difficult or impossible. Increasing complexity Large amount of test data. Number of access ports remains constant Long test application time. High speed High demand on tester’s driver/sensor mechanism. More complicated failure mechanism The key to successful testing lies in the design process.

Some Real Defects in Chips Processing defects Missing contact windows Parasitic transistors Oxide breakdown . . . Material defects Bulk defects (cracks, crystal imperfections) Surface impurities (ion migration) Time-dependent failures Dielectric breakdown Electromigration Packaging failures Contact degradation Seal leaks

Cost of Finding Defects Wafer level Packaged chip Board level System level Field level $0.01 - $0.10 $0.10 - $1 $1 - $10 $10 - $100 $100 - $1000

Errors and Faults

Logic Verification Does the chip simulate correctly? Ex: 32-bit adder Usually done at HDL level Verification engineers write test bench for HDL Can’t test all cases Look for corner cases Try to break logic design Ex: 32-bit adder Test all combinations of corner cases as inputs: 0, 1, 2, 231-1, -1, -231, a few random numbers Good tests require ingenuity

Manufacturing Test A speck of dust on a wafer is sufficient to kill chip Yield of any chip is < 100% Must test chips after manufacturing before delivery to customers to only ship good parts Manufacturing testers are very expensive Minimize time on tester Careful selection of test vectors

Missing or damaged vias Layer-layer shorts Discontinuous wires Missing or damaged vias Shorts through the thin gate oxide to the substrate or well The above leads to: Nodes shorted to power or ground Nodes shorted to each other Input floating/ output disconnected The length of the tests at the wafer level can be shortened to reduce test time based on experience with the test sequence

Testing Your Chips If you don’t have a multimillion dollar tester: Build a breadboard with LED’s and switches Hook up a logic analyzer and pattern generator Or use a low-cost functional chip tester

Testers, Test Fixtures and Test Programs

Logic Verification Principles Test benches and harnesses Regression testing Version control Bug tracking

Silicon Debug Test the first chips back from fabrication If you are lucky, they work the first time If not… Logic bugs vs. electrical failures Most chip failures are logic bugs from inadequate simulation Some are electrical failures Crosstalk Dynamic nodes: leakage, charge sharing Ratio failures A few are tool or methodology failures (e.g. DRC) Fix the bugs and fabricate a corrected chip

How to diagnose failures? Hard to access chips Picoprobes Electron beam Laser voltage probing Picosecond imaging circuit analysis Infrared imgaing Focused ion beam

Manufacturing failures Functional failures Electrical failures Failures can be: Manufacturing failures Defect or Outside parametric specifications Functional failures Chip fails under all conditions Electrical failures Malfunctions under certain conditions Shmoo plots can help to debug electrical failures in silicon

Shmoo Plots Shmoo Plot is made with voltage on X-axis and speed as Y-axis. A healthy normal chip should operate at increasing frequency as the voltages increases. The brick wall pattern suggests that the chip may be randomly initialized in one of the two states, only one of which is correct. A shmoo can also plot operating speed against temperature. In floor, leakage problem where the part fails at low frequency independent of the voltage. A finger indicates coupling problems dependent on the alignment, where at certain frequencies the alignment always causes a failure.

At cold temp. FETs are faster, have lower effective resistance, and higher threshold voltages. Normal shmoo should show speed increasing as temperature decreases. Failures at low temperature could indicate coupling or charge sharing noise exacerbated by faster edge rates. Failures at high temperature could indicate excessive leakage or noise problems exacerbated by the lower threshold voltages. Walls at either temperature indicate race conditions where the path that wins the race varies with temperature.

At 1. 8 V the chip works for clock periods of 2. 3 ns and greater At 1.8 V the chip works for clock periods of 2.3 ns and greater. At higher voltages, the chip can operate at shorter periods.

Stuck-At Faults How does a chip fail? A simpler model: Stuck-At Usually failures are shorts between two conductors or opens in a conductor This can cause very complicated behavior A simpler model: Stuck-At Assume all failures cause nodes to be “stuck-at” 0 or 1, i.e. shorted to GND or VDD Not quite true, but works well in practice

Examples

Short-circuit and open-circuit faults

Delay Fault Testing

Observability & Controllability Observability: ease of observing a node by watching external output pins of the chip Controllability: ease of forcing a node to 0 or 1 by driving input pins of the chip Combinational logic is usually easy to observe and control Finite state machines can be very difficult, requiring many cycles to enter desired state Especially if state transition diagram is not known to the test engineer

Test Pattern Generation Manufacturing test ideally would check every node in the circuit to prove it is not stuck. Apply the smallest sequence of test vectors necessary to prove each node is not stuck. Good observability and controllability reduces number of test vectors required for manufacturing test. Reduces the cost of testing Motivates design-for-test Fault coverage

Test Example SA1 SA0 A3 A2 A1 A0 n1 n2 n3 Y Minimum set:

Test Example SA1 SA0 A3 {0110} {1110} A2 A1 A0 n1 n2 n3 Y Minimum set:

Test Example SA1 SA0 A3 {0110} {1110} A2 {1010} {1110} A1 A0 n1 n2 n3 Y Minimum set:

Test Example SA1 SA0 A3 {0110} {1110} A2 {1010} {1110} n1 n2 n3 Y Minimum set:

Test Example SA1 SA0 A3 {0110} {1110} A2 {1010} {1110} n1 n2 n3 Y Minimum set:

Test Example SA1 SA0 A3 {0110} {1110} A2 {1010} {1110} n1 {1110} {0110} n2 n3 Y Minimum set:

Test Example SA1 SA0 A3 {0110} {1110} A2 {1010} {1110} n1 {1110} {0110} n2 {0110} {0100} n3 Y Minimum set:

Test Example SA1 SA0 A3 {0110} {1110} A2 {1010} {1110} n1 {1110} {0110} n2 {0110} {0100} n3 {0101} {0110} Y Minimum set:

Test Example SA1 SA0 A3 {0110} {1110} A2 {1010} {1110} n1 {1110} {0110} n2 {0110} {0100} n3 {0101} {0110} Y {0110} {1110} Minimum set: {0100, 0101, 0110, 0111, 1010, 1110}

Design for Testability Design the chip to increase observability and controllability. If each register could be observed and controlled, test problem reduces to testing combinational logic between registers. Better yet, logic blocks could enter test mode where they generate test patterns and report the results automatically. Approaches for DFT: Ad-hoc testing Scan-based approaches BIST

Ad-hoc Methods Ad-hoc test techniques as their name suggests are collections of ideas aimed at reducing the combinational explosion of testing. The Ad hoc techniques represent a bag of tricks developed over the years by designers to avoid the overhead of a systematic approach to testing. The technique classified in this category is the use of bus in a bus-oriented system for test purposes. Each register has been made loadable from the bus and capable of being driven onto the bus. The internal logic values that exist on a data bus are enabled onto the bus for testing purposes.

Common techniques for ad-hoc testing involve: Frequently multiplexers can be used to provide alternative signal paths during testing. A complete scan-based testing methodology is recommended for all digital circuits. Objective: Adherence to design guidelines and testability improvement techniques. Common techniques for ad-hoc testing involve: Partitioning large sequential circuits Adding test points Adding multiplexers Providing fro easy state reset

The goal of Ad hoc technique is to increase controllability, observability and/or predictability. Disadvantages: Ad-hoc techniques are useful for small designs. Experts and tools not available. Test generation is often manual with no guarantee of high fault coverage. Design iterations may be necessary. Ad-hoc approaches are still quite valid, process densities and chip complexities necessitate a structured approach to testing.

Monostable multivibrators: Oscillators and clocks: Test points: Employ test points to enhance controllability and observability. Initialization: Design circuits to be easily initializable. Monostable multivibrators: Disable internal one-shots during test. Oscillators and clocks: Disable internal oscillators and clocks during tests. Partitioning Counters and Shift Registers: Partition large counters and shift registers into smaller units. Partitioning of Large Combinational Circuits: Partition large circuits into small sub-circuits to reduce test generation cost. Logical Redundancy: Avoid the use of redundant logic. Global Feedback Paths: Provide logic to break global feedback paths.

Scan Design Convert each flip-flop to a scan register Only costs one extra multiplexer Normal mode: flip-flops behave as usual Scan mode: flip-flops behave as shift register Contents of flops can be scanned out and new values scanned in

Scan Path A simple means of creating a scan path consists of placing a multiplexer just ahead of each flip-flop. One input to the 2:1 MUX is driven by normal operational data while the other input is driven by the output of another flip-flop. Serial input of MUX is connected to a PI. One of the flip-flop outputs is connected to a PO pin. The MUX control line is used as mode control: It can permit parallel load for normal operation or it can select serial shift in order to enter scan mode. When scan mode is selected there is complete serial shift path from an input pin to an output pin. Scan can be full-scan or partial-scan.

For a circuit to have the scan capability, first the designer uses only D type flip-flops (DFF) with one or more clock signals, all of which are controlled from primary inputs. Once the circuit is functionally verified, the DFFs are replaced by scan flip-flops (SFF). One typical SFF is shown below, here a multiplexer and two new signals, scan-data SD and test control TC, are added to the DFF. The original data input D is stored in the flip-flop when TC is 1 and SD is stored when TC is 0.

Parallel Scan

Scannable Flip-flops

Level-Sensitive Scan Design The figure shows the general configuration for of a level sensitive scan design latch as well as a NAND/NOT implementation. D is the normal data line and C is the normal clock line. Line L1 is the normal output. Lines SI, A, B and L2 form the shift portion of the latch. SI is the shift data in and L2 is the shift data out. A and B are the two phase, non overlapping shift clocks.

Built-in Self-test Built-In Self Test (BIST): is an design technique in which parts of a circuit are used to test the circuit itself. BIST is the capability of a circuit to test itself. The goal of BIST is to add devices to a design that will allow it to test itself. Built-in self-test lets blocks test themselves Generate pseudo-random inputs to comb. logic Combine outputs into a syndrome With high probability, block is fault-free if it produces the expected syndrome

Test Controller Output Response Analyzer (ORA) Test Pattern Generator Input Isolation Circuitry Circuit Under Test Output Response Analyzer (ORA) BIST Start System Inputs System Outputs BIST Done Pass/Fail

PRSG Linear Feedback Shift Register Shift register with input taken from XOR of state Pseudo-Random Sequence Generator Step Q 111 1 2 3 4 5 6 7

PRSG Linear Feedback Shift Register Shift register with input taken from XOR of state Pseudo-Random Sequence Generator Step Q 111 1 110 2 3 4 5 6 7

PRSG Linear Feedback Shift Register Shift register with input taken from XOR of state Pseudo-Random Sequence Generator Step Q 111 1 110 2 101 3 4 5 6 7

PRSG Linear Feedback Shift Register Shift register with input taken from XOR of state Pseudo-Random Sequence Generator Step Q 111 1 110 2 101 3 010 4 5 6 7

PRSG Linear Feedback Shift Register Shift register with input taken from XOR of state Pseudo-Random Sequence Generator Step Q 111 1 110 2 101 3 010 4 100 5 6 7

PRSG Linear Feedback Shift Register Shift register with input taken from XOR of state Pseudo-Random Sequence Generator Step Q 111 1 110 2 101 3 010 4 100 5 001 6 7

PRSG Linear Feedback Shift Register Shift register with input taken from XOR of state Pseudo-Random Sequence Generator Step Q 111 1 110 2 101 3 010 4 100 5 001 6 011 7

PRSG Linear Feedback Shift Register Shift register with input taken from XOR of state Pseudo-Random Sequence Generator Step Q 111 1 110 2 101 3 010 4 100 5 001 6 011 7 111 (repeats)

Built-in Logic Block Observer (BILBO) Combine scan with PRSG & signature analysis

Boundary Scan Testing boards is also difficult Need to verify solder joints are good Drive a pin to 0, then to 1 Check that all connected pins get the values Through-hold boards used “bed of nails” SMT and BGA boards cannot easily contact pins Build capability of observing and controlling pins into each chip to make board test easier

Schematic of system test logic

Boundary Scan Example

Boundary Scan Interface The Test Acess Port has following connections: TCK: test clock TMS: test mode select TDI: test data in TDO: test data out TRST*: test reset (optional) Chips with internal scan chains can access the chains through boundary scan for unified test strategy.

Test Logic Architecture & Test Access Port

TAP Controller

Instruction Register Instruction Register is two bit long. Instruction Register specifies which data register will be placed in the scan when DR is selected. Three instructions are required: Bypass Sample/Preload Extest Optional Runbist and Intest.

Test Data Registers

Boundary Scan Register

Normal Mode: Mode_Control = 0, data passes from IN to OUT. Scan Mode: ShiftDR = 1, ClockDR = scan clock, serial data is shifted in from SIN to out SOUT. Capture Mode: ShiftDR = 0, ClockDR = one clock pulse, data on the IN line is clocked into QA. Update Mode: with QA loaded, Mode_Control = 1, UpdateDR = one clock pulse, data clock into QA is applied to OUT.

Summary Think about testing from the beginning Simulate as you go Plan for test after fabrication “If you don’t test it, it won’t work! (Guaranteed)”