Matteo Porro on behalf of the DSSC Consortium The DSSC project for XFEL: DEPFET and readout ASIC 8th International Meeting on Front End Electronics Bergamo, 26.05.2011 Matteo Porro on behalf of the DSSC Consortium

DSSC Consortium M. Porro1,2, L. Strueder1,2, G. De Vita1,2, S. Herrmann1,2, D. Muentefering1,2, G. Weidenspointner1,2, L. Andricek2,3, A. Wassatsch2,3, P. Lechner8, G. Lutz8, C. Sandow8, S. Aschauer8, P. Fischer6, F. Erdinger6, A. Kugel6, T. Gerlach6, K. Hansen7, C. Reckleben7, I. Diehl7, P. Kalavakuru7, H. Graafsma7, C. Wunderer7, H. Hirsemann7, C. Fiorini4,5, L. Bombelli4,5, S. Facchinetti4,5, A. Castoldi4,5, C. Guazzoni4,5, D. Mezza4,5, V. Re10, M. Manghisoni10, U. Pietsch9, T. Sant9 1) Max Planck Institut fuer Extraterrestrische Physik, Garching, Germany 2) MPI Halbleiterlabor, Muenchen, Germany 3) Max Planck Institut fuer Physik, Muenchen, Germany 4) Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy 5) Sezione di Milano, Italian National Institute of Nuclear Physics (INFN), Milano, Italy 6) Zentrales Institut für Technische Informatik, Universitaet Heidelberg, Heidelberg, Germany 7) Deutsches Elektronen-Synchrotron DESY, Hamburg, Germany 8) PNSensor GmbH, Muenchen, Germany 9) Fachbereich Physik, Universitaet Siegen, Siegen, Germany 10) Dipartimento di ingegneria industriale, Università di Bergamo, Bergamo, Italy

Outline Detector Requirements Detector System Overview Non-Linear DEPFET Detector working principle Detector expected performance: Speed High Dynamic Range Single Photon Resolution ASIC architecture First experimental results Conclusions

Bunch structure of the European XFEL Up to ~2700 bunches in 600 µs, repeated 10 times per second producing 100 fs X-ray pulses (~27 000 pulses/second). We want to be able to readout 1024 x 1024 pixel frames every 220 ns max bunch rate: 4.5 MHz

DSSC – Design Parameters Expected DSSC performance Energy range 0.5 … 25 keV (optimized for 0.5 … 6 keV) Number of pixels 1024 x 1024 Sensor Pixel Shape Hexagonal Sensor Pixel pitch ~ 204 x 236 µm2 Dynamic range / pixel / pulse > 6000 photons @1 keV Resolution (S/N >5:1) Single photon @ 1 keV (5 MHz) Electronics noise < 50 electrons r.m.s. Frame rate 1-5 MHz Stored frames per Macro bunch ≥ 576 Operating temperature -20˚C optimum, RT possible

System Block Diagram Readout Concept Optimum analog shaping Focal Plane Readout Concept Optimum analog shaping Immediate 8 bit digitization (9 bit for f ≤ 2.2 MHz) In-Pixel SRAM Digitized data are sent off the focal plane during 99ms gap Sensor & Front-end electronics can be switched off during the gaps

Module Box Focal Plane Overview Ladder Quadrant 1024x 1024 pixels 16 ladders/hybrid boards 32 monolithic sensors 128x256 6.3x3 cm2 DEPFET Sensor bump bonded to 8 Readout ASICs (64x64 pixels) 2 DEPFET sensors wire bonded to a hybrid board connected to regulator modules Heat spreader Dead area: ~15% Power Module Box Board Cooling P < 27 W Chip Cooling 21 cm (1024 pixels) Ladder P < 4.5 W Signals & Clocks 256x128 Quadrant unscattered beam x-y Gap K. Hansen - DESY 128 x 256 Pixel Sensor

module, mechanics and power 1-2 mW/pixel peak power  1-2 kW peak power Power cycling about 1/100 10-20 W mean power A careful thermal design is needed Voltage regulators have to deliver a lot of power in a short time First regulator board prototype ~3 mm K. Hansen - DESY Power Cycling all pixel electronics active during train phase, analog blocks sleeping during cooling phase

Every DEPFET pixel provides detection and amplification with: DSSC - Concept DEPFET Active Pixel Sensor is the first element of the Front-end Electronics Every DEPFET pixel provides detection and amplification with: Low noise Signal compression at the sensor level High speed (fully parallel readout at 1-5 MHz)

Non-Linear DEPFET Working Principle gate source drain Drain current time Internal gate The internal gate extends into the region below the source Small signals assemble below the channel, being fully effective in steering the transistor current Large signals spill over into the region below the source. They are less effective in steering the transistor current. Charge into internal gate A constant charge is injected at fixed time intervals and the internal gate regions are progressively filled In the experiment the charge is deposited at once but the DEPFET response is the same time

Sensor Simulations G. Lutz C. Sandow S. Aschauer PNS MPI-HLL e.g. cut clear/clear gate/gate/source  isolation internal gate vs. clear

Sensor - Pixel Layout hexagonal shape - side length 136 µm (A=48144 µm2) - compatible with C4 bumping @ IBM - faster charge collection - less split events Pixel Options: - Source Follower, - Drain readout Chosen pixel type: - Drain Readout technology - 2 polySi layers - 2 + 1 metal layers - 12 implantations 236 µm 272 µm 136 µm Pitchx: 204 µm Pitchy: 236 µm DEPFET

Achievable dynamic range 7 bits 0.78mV x 128 8 bits 0.78mV x 256 1 ph @1keV  1 bin = 0.78 mV 7 bits  0.78mV x 27 = 100 mV  1245 photons 8 bits  0.78mV x 28 = 200 mV  5850 photons The dynamic range depends on: The shape of DEPFET curve The number of ADC bits The gain of the first region defines the bin size

(e.g. triangular weighting DEPFET readout scheme The signal arrival time is known One measurement is composed of the difference of two evaluations: Baseline Baseline + signal A time variant filter is used In the real case some time must be reserved for the settling time of the DEPFET output both for : Signal Build up Signal clear Less than100ns out of 200ns are used to process the signal Signal injection into the internal gate time DEPFET Drain signal current DEPFET clear Pulses filtering process (e.g. triangular weighting function) XFEL pulse period = 200 ns XFEL pulse clear DEPFET baseline measurement signal settling Signal measurement readout cycle baseline measurement Signal measurement

Charge Collection signal rise time numerical simulation cylindrical approximation r = 136 µm time constants - charge collection τ ≤ 65 nsec in drain readout the collection time is in first approximation equal to the output current rise-time charge generation at r = 0 µm, z = 270 µm charge generation at r = 110 µm, z = 270 µm

System noise and resolution The noise sources of the system are: (a) Electronics Noise: DEPFET, Analog Front-End (b) Quantization noise introduced by the ADC (c) Noise of the Poisson distributed Photon Generation Process The non-linear characteristic of the DEPFET makes (a) and (b) Signal Dependent The quadratic sum of (a) and (b) must be negligible with respect to (c): the Photon Generation Noise must be dominant

From sensor simulations Electronics noise CEQ DEPFET equivalent input capacitance (decreases as the input signal increases) a, af, b physical noise sources A1 A2 A3 filter parameters (better for current readout) t filter shaping time (200ns processing time) From sensor simulations 55 fF ... 3200 fF The noise sources are almost constant The amplification decreases as the input signal increases The ENC increases with the input signal amplitude XFEL pulse period = 200 ns XFEL pulse clear DEPFET baseline measurement signal settling Signal measurement readout cycle t ENC for small signals: 45 electrons r.m.s. ENC for large signals: 2300 electrons r.m.s.

Quantization Noise 1 Electronics noise ADC bin size In the linear region (small signal) there is a correspondence 1 to 1 between ADC bins and collected photons. There is no uncertainty introduced by the ADC: THERE IS NO QUANTIZATION NOISE. Only the electronic noise counts. We set the system such that 1ph @1 keV  1 ADC bin We are sampling an already quantized input signal (the number of incoming photon is an integer)

Quantization noise 2 For high number of photons (non linear region) the ADC uncertainty increases and becomes dominant The quantization noise is the r.m.s. value of the encoding error For high number of photons the root mean square error (quantization noise) can be approximated by the number of photons attributed to the same bin divided by 12.

Quantization Noise 4 For high number of photons the quantization with noise with 8bits is always below Poisson photon generation noise The total noise of the system is dominated by the Poisson photon generation noise.

Single photon resolution 1ph @1keV  278 el. ENC ~ 45 el. r.m.s. @ 5MHz S/N ~ 6 We place the threshold in the middle of the ADC bin We assume the electronics noise Gaussian The probability to detect 1 photon instead of zero is 0.1% The probability that 1 ph signal is correctly attributed to the first bin is 99.7% It is mandatory to have a pixel-wise gain and offset correction in order to have a correct correspondence between the first photon signals and the ADC bins The ADC can trim offset and bin size for every pixel 0.1%

Noise vs. speed Operating at 2.5 MHz (acquiring a pulse every 400ns) it is possible to achieve single photon resolution @0.5keV with a S/N >6 DEPFET Noise (el.) Readout Electronics Noise (el.) Total Noise P1 1 keV ph. 0.5 keV ph. 5MHz 35 28.5 45 0.1% 6% 2.5 MHz 18 8.2 20  0 0.03% 1 MHz 10 4.7 11

dssc depfet in standard tech 1st DEPFET with signal compression DEPFETs in standard technology with basic non-linear characteristics central internal gate overflow region non-linear characteristics with two constant slopes 7-cell cluster layout Wire bonded Available in summer 2011

1st DSSC sensor production Sensor production in the DSSC techonology has started sensor layout 2 SDD-like drift rings zig-zag row-wise connections irregular routing from hexagonal sensor pixels to rectangular asic cells in copper ubm layer optional use of ubm layer as 3rd conductive layer Implemented formats: 8 x 8, 16 x 16, 128 x 256 DSSC layout detail P. Lechner, G. Lutz PNS MPI-HLL

Artist’s view of Sensor / Chip Assembly Single slope ADC 200 x 200 µm by P. Fischer

P. Fischer, F. Erdinger - Heidelberg University 8 x 8 Mini-ASIC prototype 229 x 204 µm P. Fischer, F. Erdinger - Heidelberg University

Typical FE Measurement setup ASIC FPGA board: Programming of on-chip sequencer, global timing and synchronization. Main board: Amplifiers, MUXs, bias voltages and currents, Level translation. DEPFET Carrier board: Hold ASIC + DEPFETs (CR and SFR). Providing local filtering. G. De Vita, S. Herrmann, A. Wassatsch MPI-HLL L. Bombelli, S. Facchinetti Politecnico di Milano

Readout cycle for increasing values of the input signal (single pulse). Freq = 2.57 MHz Gext = - 4.7 200 mV/div 500 ns/div Current step = 635.6 nA

Measured weighting functions A setup to pulse light onto the DEPFET has been put together in Milano Can be used to inject ‘real’ signals at known times The Weighting function of the DEPFET + Analog Front-end can be measured “A new fast filter for DEPFET readout” S. Facchinetti 13:00 A. Castoldi, C. Guazzoni Politecnico di Milano 220 ns

L. Bombelli, S. Facchinetti, Politecnico di Milano Noise with DEPFET Drain Readout, double integration, 1MHz operation: 13 e noise 1 MHz 13.0 el L. Bombelli, S. Facchinetti, Politecnico di Milano

Noise with DEPFET Drain Readout, double integration, 5MHz operation (50ns int.): 48 e noise 5 MHz 48.0 el

ADC simplified schematic Single Slope (Cramp~1pF, double buffering) Ramp generated in pixel Global Gray Coded Time Stamps @ ~1GHz Differential distribution on coplanar wave guides Fast latches in pixels Gain trim via Cramp / I-Source Offset trim with delays More bits possible by in-pixel counting Vref of Comp = Vref of Filter! Comp. switches always @ same voltage & slope!! 8 bit

ADC: Voltage → Time INL < 1LSB (limit of current source). Can be improved further. Charging current is adjustable in 5% steps (fine gain) Time Jitter has - constant part of 55ps (a bit higher than expected) - Time (=signal) dependant part, as expected Slope 201ns/V

ADC with TX/RX 5 MHz sampling rate. Same initial effect on INL

Step 1: Offset Adjustment if Noise « Bin Size: Bin Scan Zero-signal bin after offset adjustment Bin 1 Bin 0 Bin 2 CBIN0=0 CBIN1=1 CBIN2=0 Bin size Offset granularity CBIN0=0 CBIN1=1 CBIN2=0 CBIN0=0 CBIN1=1 CBIN2=0 CBIN0=0 CBIN1=1 CBIN2=0 CBIN0=0 CBIN1=0 CBIN2=1 Upper boundary CBIN0=0 CBIN1=1 CBIN2=0 CBIN0=1 CBIN1=0 CBIN2=0 Lower boundary

Ofsset trimming RMP Pixel Delay / Bin Shift Delayed RMP RMP

Error bars are from 55ps noise jitter Offset Trim ADC offset is trimmed via delay steps Average delay step has been measured to 70 ps This allows a span of 1.5 LSB (@ full speed) Error bars are from 55ps noise jitter

Pixel Circuit Details (up to Latches) Note that injection into arbitrary pixels is possible via injection bus! DEPFETs can be connected via Injectbus

ADC gain pixel comparison Gain map of the 8x8 matrix ADC The gain can be adjusted pixel by pixel preliminary matrix row Cap [F] preliminary matrix column J. Soldat, F. Erdinger – Heidelberg

J. Soldat, F. Erdinger – Heidelberg ADC Trim settings ADC gain can be adjusted pixel by pixel In the tested ASIC there are 5 fine settings for the Ramp Current For the final ASIC 9 settings are foreseen Gain adjustment wil be in the 40% range In the 9bit mode the current is reduced by a factor 2 CSH can also be adjusted of about 10% 9 bit mode 8 bit mode ADC bin count Input voltage [V] J. Soldat, F. Erdinger – Heidelberg

WF measured with on chip ADC J. Soldat, F. Erdinger – Heidelberg

Summary & Conclusions We are developing a Pixel Detector system for the European XFEL based on innovative non-linear DEPFET devices that constitute the first element of the Front-end Electronics In our fully parallel readout scheme, the signals coming from the pixels are filtered, digitized and stored in the focal plane Device and circuit simulations have shown that: It is possible to achieve 5MHz frame readout A dynamic range of at least 6000 Photons at 1keV per pixel is possible A single 1keV photon resolution (S/N>6) is reachable @ 5MHz preserving the high dynamic range Also single 0.5keV photon resolution is achievable @ 2.5Mhz Measurements on first ASIC blocks show performance in good agreement with simulations and a noise below 50 el. r.m.s. At the maximum operating speed First DEPFET with signal compression will be available soon The first DSSC Sensor production comprising full-size sensors has started

SPARE SLIDES

Non-Linear DEPFET Characteristic Output voltage (SF readout) vs. input charge (CS=0.5pF, RS=100k, ID=110mA): 220 mV for 360fC (8000 X-rays @ 1 keV) Highest sensitivity: 2.8 µV/electron ( 6.2V output swing without compression!) Lowest sensitivity: 0.05 µV/electron

Quantization Noise 1 We assume not to have charge sharing among neighbouring pixels We have to sample the output response of the DEPFET, which is: Non linear over a high dynamic range Discrete because the input of incoming photon is an integer We set the size of the ADC bins equal to the output swing of the pixel given by the first collected 1keV Photon (278 el) We have to distinguish two cases: Very low number of incoming photons: linear region High number of collected photons

Interface to Data Generator, ADC Testsetup Analog Power & Input CLK & RMP Signals Pad Power Drivers Digital Output Digital Power Core Digital Power GCC & TX Decoupling Caps ADC Motherboard Interface to Data Generator, MS-Oscilloscope & Powersupplies DUT – Board 4 Layer PCB 2 different GND domains

Minimum signal Readout cycle for minimum value of the input signal (Isignal = 100 nA); waveforms are averaged. Freq = 2.57 MHz Gext = - 24.74 200 mV/div 100 ns/div On board output variation = 124 mV On chip output variation = 5.01 mV (theoretical output = 6.21 mV)

ADC: 1st Test Chip 1st ADC Test Chip: 1 Gray Code Counter 1 TX & 64 RX: Source-Coupled Logic 13-mm 8-bit sCPWG pixel Timing Diagram Number of Photons Max

1st ADC Test Chip: Measurements Circuit works as expected 800 MHz operation No missing Codes DNL < 0.4 LSB Rms jitter < 14 ps Last pixel delayed by 470ps CLK……....... 800 MHz Binnom ......... 625 ps Resol. .......... 31.25 ps

ADC Operation Single Slope (Cramp~1pF, double buffering) Ramp generated in pixel Global Gray Coded Time Stamps @ ~1GHz Differential distribution on coplanar wave guides Fast latches in pixels Gain trim via Cramp / I-Source Offset trim with delays More bits possible by in-pixel counting Vref of Comp = Vref of Filter! Comp. switches always @ same voltage & slope!!

ASIC - Timings for Current Readout 200ns readout cycle – 5Mhz Thermal noise is dominant A1=2 for trapezoidal WF “a” extracted from DEPFET measurements and ASIC simulations CEQ=55fF from simulations t 35-435 ns (5MHz – 1MHz) clear DEPFET baseline measure signal settling Signal measure 65 ns <35 ns 65 ns <35 ns XFEL pulse clear DEPFET baseline measure signal settling Signal measure 1ms readout cycle – 1MHz 65 ns t=435 ns XFEL pulse t=435 ns

ADC: 1st Test Chip 1st ADC Test Chip: 1 Gray Code Counter 1 TX & 64 RX: Source-Coupled Logic 13-mm 8-bit sCPWG pixel Timing Diagram Number of Photons Max

1st ADC Test Chip: Test setup Fancy PCB + Fast Test equipment (pulser + scope)

1st ADC Test Chip: Measurements Circuit works as expected 800 MHz operation No missing Codes DNL < 0.4 LSB Rms jitter < 14 ps Last pixel delayed by 470ps CLK……....... 800 MHz Binnom ......... 625 ps Resol. .......... 31.25 ps

Pixel Read-out channel ASIC with 4.096 readout channels! Each readout channel has an Analog Front-end, S&H, ADC, RAM and injection circuit 2 Front-end alternatives: Source Follower (SF) and Drain Readout (DR) share the Trapezoidal Filter Analog Front-end ADC RAM S&H

WF measurement Preliminary results Processing time 388 ns

DR - Filter Works as expected More detailed studies under way Gext = - 4.7 1 Reset 2 First integration 3 Flip phase 4 Second Integration 5 Hold 200 mV/div 200 ns/div Input current step 2 4 1 3

1st ADC Test Chip: Measurements Circuit works as expected 800 MHz operation No missing Codes DNL < 0.4 LSB Rms jitter < 14 ps Last pixel delayed by 470ps CLK……....... 800 MHz Binnom ......... 625 ps Resol. .......... 31.25 ps

ADC: Reminder of Concept Single Slope ADC successfully used in multi-ADC applications: very simple architecture minimal analog content shared functionalities minimal area requirements (per channel) In our case: Local ramp generation Time stamp distribution on shielded coplanar waveguides using differential signals Tedja et al., IEEE SSC 1995 Yang et al., CICC 1998 Kleinfelder et al., IEEE SSC 2001 Hwang et al., SPIE 2007 Varner et al., NIMA 2007 Delagnes et al., IEEE TNS 2007  Da Silva et al., IEEE NSS 2007 Crooks et al., IEEE Sensors 2008

ADC: 1st Test Chip 1st ADC Test Chip: 1 Gray Code Counter 1 TX & 64 RX: Source-Coupled Logic 13-mm 8-bit sCPWG pixel Timing Diagram Number of Photons Max

How do split events influence 1keV single photon resolution? Charge collected as a function of the distance of the interaction point form the pixel border

TeSCA Simulations 97% collected for d=15µm 99.5% collected for d=20µm Split events 2 TeSCA Simulations 97% collected for d=15µm 99.5% collected for d=20µm

Split events 3 We assume that a single 1keV photon interacts with a pixel We center our problem on the interaction pixel and consider all the neighbouring pixels The border among three pixels is ignored

The threshold is in the middle (138 el.) Split events 4 A single 1keV (277 el.) Photon interacts with the central pixel in a random position The threshold is in the middle (138 el.) Different noise levels corresponding to different readout speed The position resolution is limited by the pixel size 45 el. 20 el. 11 el. 0 Photons 2% 0.84% 0.48% 1 Photon in right pixel 94.7% 98% 98.9% 1 Photon in wrong pixel 0.8% 0.3% 0.2% 1 Photon in total 95.5% 98.3% 99.1% 2 Photons 0.81% 0.45%

Radiation Hardness At 1Mrad a threshold voltage shift of 6V has been measured with an oxide thickness of 180nm

Step 1: Overview of Procedure for Setting Offset and Gain Procedure for full calibration in Laboratory: Offset adjustment using dark frames (e.g. assign zero signal to ADC bin 1) Gain adjustment using X-ray line (e.g. 55Fe source) Possibly: Offset re-adjustment using dark frames

Comment on Determination of Peak Position Offset and gain adjustment require determination of position of signal peak System output is ADC value System noise ➟ output varies (peak has finite width) Finite resolution of signal adjustment e.g. offset: granularity ΔSHIFT = 1/10 bin 1/5 in this picture. 1/10 in the real system depending on noise level: different methods to determine center of signal peak, e.g.: noise « bin size: scan for bin boundaries in steps of granularity (most conservative) noise < bin size: maximize probability of signal in selected bin by multiple measurements for different adjustments noise comparable to or large than bin size: fit ADC distribution of signal peak (if shape known) weighted average

Step 1: Offset Adjustment if Noise « Bin Size: Bin Scan Zero-signal bin after offset adjustment Bin 1 Bin 0 Bin 2 CBIN0=0 CBIN1=1 CBIN2=0 Bin size Offset granularity CBIN0=0 CBIN1=1 CBIN2=0 CBIN0=0 CBIN1=1 CBIN2=0 CBIN0=0 CBIN1=1 CBIN2=0 CBIN0=0 CBIN1=0 CBIN2=1 Upper boundary CBIN0=0 CBIN1=1 CBIN2=0 CBIN0=1 CBIN1=0 CBIN2=0 Lower boundary

Step 1: Offset Adjustment if Noise < Bin Size: Max. Prob. PC,BIN1∼0.9 Zero-signal bin after offset adjustment max(PC,BIN1) PC,BIN1∼1 PC,BIN1∼0.3 PC,BIN1∼0.3

Step 1: Offset Adjustment if Noise < Bin Size: Max. Prob. Optimized Example: Sensor noise = 25 ENC (about 10% of bin size) Offset disturbance = -0.23 LSB maximize counts in bin 4 3.9 LSB 4.2 LSB 4.5 LSB number of counts in bin 4 as function of offset ➟ position (and width) of peak