CSE 460: Switching Theory David M. Zar Computer Science and Engineering Washington University Spring HS 1-58 Read HS 1-58

1-2 - David Zar - 9/11/2015 Inroduction n Administrivia »Meet Monday/Wednesday 2:30-4:00 p.m. in Cupples II 202 »Final Exam Date: Monday May 10 6:00-8:00 p.m. »Class web site »Text book Logic Synthesis and Verification Algorithms by Gary D. Hachtel and Fabio Somenzi, Kluwer 1996 n Who am I? »David M. Zar »Bryan Hall 307C »

1-3 - David Zar - 9/11/2015 Syllabus n Combinational Techniques »Boolean Algebras »Two-Level Logic Synthesis »Heuristic Minimization »Binary Decision Diagrams n Fault Analysis n Sequential Techniques »Models of Sequential Systems »Synthesis and Verification »Finite Automata »Asynchronous Circuits n Multi-Level Logic Synthesis n Other fun things like Testability, BIST, etc.

1-4 - David Zar - 9/11/2015 Grading and Reading n So you want a grade, huh? »20% Homework »25% Each of Two Midterm Exams »30% Final Exam n READ! »Reading assignments are not “graded” but the book is very in depth and not reading will hurt (although you may think that upon the first read, that hurts). »Chapters 1 and 2 are some background and overview. We will not cover the graph theory right now, but will do just- in-time delivery of that material, later. Still, review it, especially if you are rusty or have never seen it.

1-5 - David Zar - 9/11/2015 CoE260 and Moore’s Law n CoE260 introduced fundamentals of digital logic »Small numbers of inputs and outputs »Small numbers of gates »Synthesis performed manually n Modern digital systems can be huge by comparison »In 1965, Gordon Moore ( ) predicted that the number of transistors per IC would double every 18 months »He predicted the trend would hold through 1975; It seems to still be holding »Often times many technological advances with exponential growth are said to follow “Moore's Law”

1-6 - David Zar - 9/11/2015 VLSI Today n Minimum feature size has shrunk considerably: Notes: »Xeon has 1 MB L3 cache »Pentium M is a low-power device »Itanium is a 64-bit processor with up to 6 MB L3 cache »P4 Extreme Edition has 512KB L2 cache, 2 MB L3 cache, 1066 MHz FSB. »Core2 Duo/Quad include 2MB/8MB L2 cache, 1066 Hz FSB

1-7 - David Zar - 9/11/2015 How about Transistors? n The following table comes from data on the Intel web site:

1-8 - David Zar - 9/11/2015 Issues for Such Large Designs n Developing digital solutions of this magnitude involves serious challenges »Large numbers of developers »Many degrees of freedom »Advance of technology makes for short product revenue life »High pressure to reduce time-to-market »Manual synthesis is infeasible due to large numbers of gates n As a result, some degree of automation is a necessity n Software exists to address many areas of digital logic designs including: »Design management »Synthesis (i.e. HDL into logic) »Verification (i.e. simulation, test generation) »Optimization »Placement and Routing n We will not consider the development of automation software but will cover some fundamentals on which they are based n Most engineers in digital design will never author such software, but understanding principles is extremely important for proper usage of any tool

1-9 - David Zar - 9/11/2015 VLSI Implementation Styles n Metal Oxide Semiconductor (MOS) processes are the extremely popular for digital logic implementation primarily because of low power consumption CMOS (Complimentary MOS, utilizing n- and p-channel transistors on the same chip) is dominant today n MOS transistor can be thought of as a voltage controlled switch »Switch between source and drain is closed or opened depending on gate voltage »n-channel transistor is “closed” (conducting) when a high voltage is placed on its gate and “opened” (non-conducting) with a low gate voltage

David Zar - 9/11/2015 More MOS Transistors… »p-channel transistor is the opposite, closed when a low voltage is placed on its gate and opened with a high voltage n Logic gates can be realized by interconnections of these transistors: »An inverter opens the p-channel transistor and closes the n-channel when the input is high, and has the opposite affect when the input is low »In a NOR gate, the output path to high voltage is present only when both A and B are low; otherwise at least one path to ground exists

David Zar - 9/11/2015 Design Opportunities n Design components are commonly distinguished by the level of customization required in the final component: » Full Custom Design : Every circuit in the component is optimized for its purpose in this design » Semi-Custom Design : Circuit is assembled from pre-designed and pre-characterized subcircuits » Programmed Design : Circuit is realized by programming a standard part such as nonvolatile memory, PLA, or FPGA

David Zar - 9/11/2015 Optimality Tradeoffs n A common goal is to achieve an optimal or near-optimal design n To achieve such a goal, we need some notion of what it means to be “optimal” n A commonly used approach is to minimize some convex function of: » Area occupied by logic gates and interconnect » Critical Path Delay, the longest delay through the circuit » Degree of Testability, the percentage of faults covered by some number of input test vectors » Power consumed by the logic gates n This optimization is usually constrained by physical considerations such as maximum area used, maximum power consumed, etc. n Generally these criteria are interrelated and cannot be simultaneously optimized

David Zar - 9/11/2015 Optimality Example n Changes that cause the design point to move parallel to one axis and toward the other are “tradeoff-free,” improving one criteria while not affecting the other n Changes that move the design point along the tradeoff curve are optimal tradeoffs, sacrificing on one criterion to gain on another For example, the set of all possible combinations of area A and delay  can be divided into those that are achievable (or feasible ) with a given technology and those that are unachievable (or impossible ) n The curve that separates these two regions and satisfies constraints is the optimal tradeoff curve