PowerBench Programmable Power Supply Final presentation – part B March 22 th, 2009 Gregory Kaplan Dmitry Babin Supervisor: Boaz Mizrahi HS DSL

Topics Overview –Basic reminder –Targets and expectations –Top-level survey of the implementation Implementation –Schematics –CAD simulations Layout –Design guidelines and overview –Features of interest Mechanics –Thermal –UI Future developments

Active load Power supply Control unit User interface for standalone operation LCDKeysLEDs User interface DUTDUT Measurement unit Overview A brief reminder Overview A brief reminder

Power supply unit capabilities –Variable source/sink operation –Four independent outputs –Configurable current limits –Fast load transient simulation –DRAM-like power consumption simulation –Two-way communication with a PC Overview Design targets vs projected capabilities I  Overview Design targets vs projected capabilities I

Source operation –Output voltage: 0.9 to 12.6 V –Output current: 0 to 3.5 A –Programming resolution: < 5 mV –Ripple and noise: < 20 mV peak-to-peak –Settling time: < 1 ms Load operation –Input current: 0 to 3.5 A –Programming resolution: < 1 mA –Fast (< 100 ns) transient load simulation Overview Design targets vs projected capabilities II  Overview Design targets vs projected capabilities II

DC-DC Converter Post regulator ADC Voltage Sense DAC Current Sense Output FPGA Controller Block Output setting Input voltage sense feed- forward Tempe- rature Current limit PWM Microprocessor Overview Control Scheme ADC Auxiliary Voltage Sense Overview Control Scheme

Overview Source/Sink/Measurement Module 1 (Outputs 1, 2) OUTPUT 1 RETURN 1 MIC4102YM TO/FROM FPGA OUTPUT 2 RETURN 2 MIC4102YM MOSFET Driver V DD LT2296- CUP LT2296- CUP A/D Converter 2 PWM 1 SOURCE/SINC V DD 2 ADC CONTROL 4 SPI 14 ADC DATA 2 ADC CONTROL 1 CLR 1 SOURCE/SINC 4 SPI AD Ch 10-bit ADC AD5415YRUZ D/A Converter Overview Source/Sink/Measurement Module 1 (Outputs 1, 2

Overview Source/Sink/Measurement Module 2 (Outputs 3, 4) OUTPUT 3 RETURN 3 MIC4102YM TO/FROM FPGA OUTPUT 4 RETURN 4 FAN3227TMX MOSFET Driver V DD LT2296- CUP LT2296- CUP A/D Converter 2 PWM 1 SOURCE/SINC AD5415YRUZ V DD D/A Converter 2 ADC CONTROL 4 SPI 14 ADC DATA 2 ADC CONTROL 1 CLR AD Ch 10-bit ADC 4 SPI Overview Source/Sink/Measurement Module 2 (Outputs 3, 4)

USB Port 16 DATA USB CONTROL 2 2Mbit SPI Flash SPI DATA IN, OUT, CLK 3 SPI CS,WP,HOLD 2 PROG_B*,DONE* ADC Output ADC Control PWM SPI * Dedicated conf pins 16 DATA USB High-Speed USB 5 USB CONTROL USB Control CY7C68013A -100AXC M25P20 -VMN6 Xilinx SPARTAN 3-E XC3S250E-4-PQ208 Microchip PIC18F87J50 -I/CT Overview Control Module TO/FROM SSM MODULE DAC 2 1 Real Time Clock Temperature monitor (2 devices) LM75 CIM-5 RTC-8564JE I2CI2C 4 Keypad Graphic LCD Module Optrex F-51553GNBJ -LW-AEN PB1-PB PB0 Overview Control Module

Overview Power flow – Control Module Overview Power flow – Control Module Universal Input Up to 100W ECM V LM3668SD LTC4090 FAN4855MTC Li-ion V (optional) 3.3V 5V AC/DC Converter DC/DC Converter + Battery Charger 3.3V Buck-Boost DC/DC Booster VDD Microchip PIC18F87J50 Graphic LCD Module Optrex F-51553GNBJ -LW-AEN CY7C68013A M25P20 RTC-8564JE Xilinx SPARTAN 3-E 2.5V 1.2V VDD Vaux Vcore VDD Up to 85mA Up to 15mA Up to 0.8mA Up to 222mA More than 100mA Up to 42mA BR1255 Small Li battery (optional) 5V, V BAT +0.3V or V BAT TPS73001 TPS V LDO 1.2V Buck 5V, V BAT +0.3V or V BAT

Overview Power flow - Source/Sink/Measurement Module Universal Input Up to 100W ECM100 AC/DC Converter 15.8V (Direct from AC) OUTPUT 1 RETURN 1 MOSFET Driver 14 bit ADCDAC 10 bit ADC DAC 14 bit ADC 3.3V ×4 Overview Power flow - Source/Sink/Measurement Module 5V, V BAT +0.3V or V BAT ADP1611 Boost LT3580 Inverter 15.8V (From AC or battery) -15.8V (From AC or battery)

Topics Overview –Basic reminder –Targets and expectations –Top-level survey of the implementation Implementation –Schematics –CAD simulations Layout –Design guidelines and overview –Features of interest Mechanics –Thermal –UI Future developments

Implementation 3 separate boards from the start: –“Digital” – control board –“Analog” – sink/source/measurement (SSM) –“Panel” – user interface (UI) The design process: –Component selection –Schematics –Simulation –Layout

Implementation – Schematics Introduction Environment: –OrCAD Capture 16.0 –Custom library for all the parts –Hierarchical design –Use of “instances” where applicable Component selection –Priority to Zoran stock when possible –Minimum different components –All ICs in “accessible” packages (no DFN or BGA except when unavoidable) –Price Design guidelines –Clear schematics with maximum relevant information –Maximum flexibility in the post-layout stage –Scalability and “overheads”

Implementation – Schematics Control Module : Clock Clock buffer and oscillator running at 24MHz Alternate clock sources (crystals) can be used for the MCU and USB chips

Implementation – Schematics Control Module : Power distribution I A dedicated power manager IC select from either high- voltage DC line, battery or USB power sources, converting them to a voltage around the battery voltage or 5V It also charges the battery when possible (and permission is granted by the MCU)

Implementation – Schematics Control Module : Power distribution II The 3.3V converter masters other secondary converters (the 5V, 2.5V and 1.2V ones): –while 3.3V rail is low, all secondary converters are turned off (including the 3.3V converter itself!) –while 3.3V rail is high, secondary converters may be turned on/off by the MCU (if 3.3V is turned off, the system may be turned on only by a button)

Implementation – Schematics Control Module : Connectors Connection to the other boards –120-pin 0.1” connector to the SSM module –40-pin 0.1” connector to the UI module End-user interface –USB-B connector Debug and programming –JTAG –ICSP –12-pin and 14-pin debug ports on the USB chip –2 x 38-pin MICTOR connectors –2 SMA-type connector footprints

Implementation – Schematics Control Module : Connectors The SSM module connector –Signal speed of up to 100MHz –Adequate grounding around clock lines –No crossing between signals (will be shown later in the layout stage) –“Fast” lines spread between “slow” lines

Implementation – Schematics SSM Module : DC-DC Buck Converter A buck DC-DC converter –Input: 15.8V –Output: 0..X V –Maximum operating frequency: Y KHz –Estimated efficiency: Z% –Can work both in continuous and discontinuous conduction modes –High-frequency spikes are rejected by the output ferrites

Implementation – Schematics SSM Module : Positive LDO A low-dropout post-regulator –Input: X..Y V –Output: 0..X V –Loop bandwidth: X MHz –Actively controlled by the DAC output –Proposed mode of operation: constant power dissipation –Smoothes the buck converter’s output ripple

Implementation – Schematics SSM Module : Active load A varying load –Resistance varies from X Ohm to Y Ohm –Loop bandwidth X MHz –Desired current is set by the output of the DAC –Too much output inductance can interfere with operation

Implementation – Schematics SSM Module : Mode switching A low-resistance circuit used to switch between the source and sink modes –Resistance X mOhm –Switching time Y msec

Implementation – Schematics SSM Module : Current sensing A fully differential instrumentation amplifier reads the voltage across a 30mOhm resistor in the power path, amplifying it by X times before feeding a differential pair to the ADC. Amplifier bandwidth is 1 MHz.

Implementation – Schematics SSM Module : Power distribution example Generation of the -15.8V supply rail from battery or the DC input and its distribution to the different channels

Implementation – Schematics SSM Module : DC-DC Cuk Converter A converter that inverts the +15.8V power input to generate a V output:

Implementation – Schematics SSM Module : 4-Ch 10-bit ADC Measuring the outputs of the DC-DC converters before the post-regulator in each of the 4 channels

Implementation – Simulations Introduction Environment: –PSPICE –LTSPICE –Texas Instruments simulator Simulation goals: –Switching times –Stability (open + closed loop) –Voltage levels –Reliability Key simulations: –Power ORing circuits –All amplifier circuits (LDO, active load, active filters) –All analog switches Major obstacles –Highly non-linear circuits –Unknown external load parameters

Implementation – Simulation Active load – open loop response Below is shown a PSPICE simulation of the open loop response of the active load circuit: –Load current: 200mA –DUT voltage: 12.6V –0-dB point – 4Mhz –Phase margin: 71.4deg –Gain margin : 25.5dB Green: Open loop gain (dB) Red: Open loop phase (deg)

Implementation – Simulation Active load – transient behavior Below is shown a PSPICE simulation of the transient behavior of the active load circuit: –Load current step: 1A with a rise/fall time of 500ns (2MHz) –DUT voltage: 12.6V –Overshoot: 95mA –Settling time: 300ns to within 5% –Assumed lead inductance of 0.5uH and contact resistance of 150mOhm Green: Control input voltage Red: DUT current

Implementation – Simulation Instrumentation amplifier – frequency response Below is shown a PSPICE simulation of the frequency response of the instrumentation amplifier used as the active filter in the current sense circuit: –Bandwidth: 1MHz –Maximum ripple within bandwidth: 0.4dB –DC gain: 19.5dB Green: Control input voltage Red: DUT current

Implementation – Simulation Mode switch circuit - transient Below is shown a PSPICE simulation of the frequency response of the switching circuit used to select between the source and sink functions –Switching time: –Maximum resistance:

Implementation – Debug Control module: –ICSP port –JTAG port –2 MICTOR connectors in parallel to most major data and control lines –2 free Cypress ports available for debugging (test points) –4 DIP switches and 4 LEDs on dedicated debug IOs of FPGA –Ground test points spread across the board SSM module –Ground test points spread across the board –Most components in packages with leads to enable easy connection

Topics Overview –Basic reminder –Targets and expectations –Top-level survey of the implementation Implementation –Schematics –CAD simulations Layout –Design guidelines and overview –Features of interest Mechanics –Thermal –UI Future developments

Layout Introduction Environment –OrCAD 16.0 netlists –Mentor PCB Layout tools Design Guidelines –Signal reliability (minimize crosstalk and parasitics) –EM compatibility (low emissions and susceptibility) –Thermal considerations –Mechanical considerations

Layout Control Module - Overview 167x168 mm 6 layers 1 oz copper Stackup: 1.Component side: signal 2.Ground 3.Signal + low power 4.Signal + low power 5.Power 6.Print side: signal Components on both sides Connection to SSM module Power Connection to UI module and debug interfaces Debug Control hardware

Layout SSM Module - Overview

Layout SSM Module – Signal path

Layout SSM Module – Power path

Layout SSM Module – Power planes

Layout UI Module

Layout SSM Module – Overview 157x168 mm 8 layers 1 oz copper Stackup –Component side: signal –Layer 2: power –Layer 3: signal (horizontal) –Layer 4: signal (vertical) –Layer 5: GND –Layer 6: differential striplines –Layer 7: GND –Print side: signal Components on both sides

Layout UI – Overview 110x230 mm 2 layers 1 oz copper Stackup –Component side: signal + power –Print side: signal + power Components on both sides

Topics Overview –Basic reminder –Targets and expectations –Top-level survey of the implementation Implementation –Schematics –CAD simulations Layout –Design guidelines and overview –Features of interest Mechanics –Thermal –UI Future developments

Mechanical Design Introduction 3 boards – one system case –Hard plastic (ABS) case: 260x180x105 mm –Battery and power supply included –Cutouts: user interface and connectors (power, USB) Environment –Google SketchUp 6.0

Mechanical Design User Interface Graphic 128x64 LCD (up to 8x16 text characters) 4x4 Keypad + ‘Enter’ key 4 ‘soft’ keys under the LCD 4 LED indicators Power on / battery on indicator Buzzer

Mechanical Design Thermal characteristics Characteristics: –When sinking current, each channel can generate up to 25W of heat –When sourcing current, losses of up to 3W per channel are expected –Self-power circuits exhibit efficiencies of around 90%, meaning thermal losses on the order of up to several watts overall Solutions: –Ventilation holes throughout the case –All heat-generating components chosen so that they can withstand the temperature rise –Big custom-made heatsink attached to the transistors of the source/sink stages –External fans will be added to the case –Constant temperature monitoring by the MCU enable shutdown in case of overheating

Statistics 1 project 2 partners 3 boards 10 months ~60 breakfasts at Zoran 129 different electronic components ~1700 man-hours 996 nets 1221 total electronic components 4017 solder pads bytes in project folder

From now on: Looking for code monkeys