S4525A Peripherals & Enhanced FLASH 1 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 1 Peripherals & Enhanced FLASH New Peripherals and Demo Enhanced FLASH PIC16F87X and PIC16F62X Enhanced FLASH PIC16F87X and PIC16F62X

S4525A Peripherals & Enhanced FLASH 2 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 2 Peripherals & Enhanced FLASH PIC16F87X Features at a Glance l 8K x 14 FLASH Program Memory l Typ E/W l Byte/Word Read/Write at V DD l 256 x 8 EEPROM Data Memory l Min. 100K E/W l 368 x 8 Data Memory (RAM) l 33 I/O ports l 25mA sink/source l 3 Timers l bit l bit l 10-bit A/D l 8K x 14 FLASH Program Memory l Typ E/W l Byte/Word Read/Write at V DD l 256 x 8 EEPROM Data Memory l Min. 100K E/W l 368 x 8 Data Memory (RAM) l 33 I/O ports l 25mA sink/source l 3 Timers l bit l bit l 10-bit A/D l Two Capture/Compare/PWMs l USART l 9-bit addressable l High Speed Enhanced SPI  l All 4 SPI modes supported l Microwire  Support Master I 2 C  l Hardware Write to I 2 C devices In-Circuit-Serial Programming  l In-Circuit-Debugger l Parallel Slave Port

S4525A Peripherals & Enhanced FLASH 3 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 3 Peripherals & Enhanced FLASH PIC16F62X Features at a Glance l 18-pin package l Up to 2K x 14 FLASH Program Memory l Typ E/W l Byte/Word Read/Write at V DD l 128 x 8 EEPROM Data Memory l Min. 100K E/W l 224 x 8 Data Memory (RAM) l 16 I/O ports l 25mA sink/source l 18-pin package l Up to 2K x 14 FLASH Program Memory l Typ E/W l Byte/Word Read/Write at V DD l 128 x 8 EEPROM Data Memory l Min. 100K E/W l 224 x 8 Data Memory (RAM) l 16 I/O ports l 25mA sink/source l 3 Timers l bit l bit l Capture/Compare/PWM l USART l 9-bit addressable l High Speed l 2 Comparators In-Circuit-Serial Programming  l Internal RC Oscillator

S4525A Peripherals & Enhanced FLASH 4 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 4 Peripherals & Enhanced FLASH Enhanced FLASH Program Memory l The original FLASH concept had bulk erase and an EPROM-like write. l Most MCU-based FLASH devices have bulk/block erase and block writes. l Microchip offers the best of both worlds: l Byte write operation (preceded by erase before write). l Bulk erase operation. l This is Enhanced FLASH. l FLASH Program Memory. l 1,000 erase/write cycles minimum. l Data EEPROM Memory. l 100,000 erase/write cycle minimum. l The original FLASH concept had bulk erase and an EPROM-like write. l Most MCU-based FLASH devices have bulk/block erase and block writes. l Microchip offers the best of both worlds: l Byte write operation (preceded by erase before write). l Bulk erase operation. l This is Enhanced FLASH. l FLASH Program Memory. l 1,000 erase/write cycles minimum. l Data EEPROM Memory. l 100,000 erase/write cycle minimum.

S4525A Peripherals & Enhanced FLASH 5 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 5 Peripherals & Enhanced FLASH FLASH Program & Data EEPROM: Programming/Erase Operation l Program timing controlled by an internal RC oscillator. l Timeout set for ~2mS per word. l When timeout occurs, EEIF flag is set. l Read operation has to be done to verify write. l Write operation sequence has to be followed for each location: l Write 0x55 then 0xAA to EECON2, then set write flag. l Failure to follow sequence aborts write operation. l Advantage: Prevents inadvertent write operations. l Program timing controlled by an internal RC oscillator. l Timeout set for ~2mS per word. l When timeout occurs, EEIF flag is set. l Read operation has to be done to verify write. l Write operation sequence has to be followed for each location: l Write 0x55 then 0xAA to EECON2, then set write flag. l Failure to follow sequence aborts write operation. l Advantage: Prevents inadvertent write operations.

S4525A Peripherals & Enhanced FLASH 6 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 6 Peripherals & Enhanced FLASH FLASH Program and Data EEPROM Memory FLASH Program Memory 8K X 14 S. F. R. 256 X 8 Data EEPROM Memory EEADRH EEADR EEDATH EEDATA EECON1 EECON

S4525A Peripherals & Enhanced FLASH 7 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 7 Peripherals & Enhanced FLASH FLASH Program & Data EEPROM: Special Function Registers l EEDATA (10Ch) l Holds data for Data EEPROM. l Holds 8 LSbs of data for Program FLASH. l EEADR (10Dh) l Holds address for Data EEPROM. l Holds 8 LSbs of address for Program FLASH. l EECON1 (18Ch), New Bit EEPGD l EEPROM Read/Write Control Register. l EECON2 (18Dh) l Not a physically implemented register, reads all ‘0’s. l Used exclusively for the memory write sequence. l EEDATA (10Ch) l Holds data for Data EEPROM. l Holds 8 LSbs of data for Program FLASH. l EEADR (10Dh) l Holds address for Data EEPROM. l Holds 8 LSbs of address for Program FLASH. l EECON1 (18Ch), New Bit EEPGD l EEPROM Read/Write Control Register. l EECON2 (18Dh) l Not a physically implemented register, reads all ‘0’s. l Used exclusively for the memory write sequence.

S4525A Peripherals & Enhanced FLASH 8 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 8 Peripherals & Enhanced FLASH FLASH Program & Data EEPROM: Special Function Registers l EEDATH (10Eh) l Used exclusively for Program Memory operations. l Holds the 6 MSbs of the data value. l EEADRH (10Fh) l Used exclusively for Program Memory operations. l Holds the 5 MSbs of the address. l The PIC16F87X devices can calculate program memory checksums. l Checksum calculation allowing program memory integrity. l EEDATH (10Eh) l Used exclusively for Program Memory operations. l Holds the 6 MSbs of the data value. l EEADRH (10Fh) l Used exclusively for Program Memory operations. l Holds the 5 MSbs of the address. l The PIC16F87X devices can calculate program memory checksums. l Checksum calculation allowing program memory integrity.

S4525A Peripherals & Enhanced FLASH 9 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 9 Peripherals & Enhanced FLASH FLASH Program & Data EEPROM: EECON1 Register EEPGD WRERR WREN WR RD bit7bit0 EEPGD: Program / Data EEPROM Select Bit 1 = Accesses Program Memory 0 = Accesses Data Memory WRERR: EEPROM Error Flag Bit 1 = A write operation is prematurely terminated 0 = The write operation completed WREN: EEPROM Write Enable Bit 1 = Allows write cycles 0 = Inhibits write to the EEPROM WR: Write Control Bit 1 = Initiates a write cycle (cleared by hardware only) 0 = Write cycle to the EEPROM is complete RD: Read Control Bit 1 = Initiates a read cycle (cleared by hardware only) 0 = Read cycle from the EEPROM is complete

S4525A Peripherals & Enhanced FLASH 10 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 10 Peripherals & Enhanced FLASH FLASH Program Memory: Three Programming Modes  Low Voltage ICSP  mode (Default mode): l Programming at V DD (typically 5V). l RB3/PGM pin dedicated as Program Mode Select. · High Voltage ICSP mode: l High voltage (13V) required on MCLR/V PP pin. l Same ICSP mode as in many other PICmicro ® MCUs. l RB3/PGM pin can be used as normal I/O. ¸ Internal Program Write mode: l Single word writes during program execution. l Example: Calibration constants etc.  Low Voltage ICSP  mode (Default mode): l Programming at V DD (typically 5V). l RB3/PGM pin dedicated as Program Mode Select. · High Voltage ICSP mode: l High voltage (13V) required on MCLR/V PP pin. l Same ICSP mode as in many other PICmicro ® MCUs. l RB3/PGM pin can be used as normal I/O. ¸ Internal Program Write mode: l Single word writes during program execution. l Example: Calibration constants etc.

S4525A Peripherals & Enhanced FLASH 11 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 11 Peripherals & Enhanced FLASH FLASH Program Memory: Low Voltage ICSP Mode (Default) RB3 RB6 RB7 V SS V DD CLK DATA V DD PIC16F87X or PIC16F62X Enters LV Programming Mode MCLR PIC16F87X or PIC16F62X V DD

S4525A Peripherals & Enhanced FLASH 12 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 12 Peripherals & Enhanced FLASH FLASH Program Memory: Low Voltage ICSP Mode (Default) Sequence: l Low Voltage Programming (LVP) bit in the Configuration Word has to be ‘1’. l RB3/PGM pin is automatically used as a dedicated sense line to enter LV ICSP mode. l V DD and MCLR have to be at same voltage (5V typically). l RB3/PGM pin going from a logic low to high causes LV ICSP. In LV ICSP mode: l RB6 and RB7 are used as serial clock/data lines to serially program the PIC16F87X/PIC16F62X. l All programming operations are enabled. l Exception: LVP bit cannot be re-programmed to ‘0’. Sequence: l Low Voltage Programming (LVP) bit in the Configuration Word has to be ‘1’. l RB3/PGM pin is automatically used as a dedicated sense line to enter LV ICSP mode. l V DD and MCLR have to be at same voltage (5V typically). l RB3/PGM pin going from a logic low to high causes LV ICSP. In LV ICSP mode: l RB6 and RB7 are used as serial clock/data lines to serially program the PIC16F87X/PIC16F62X. l All programming operations are enabled. l Exception: LVP bit cannot be re-programmed to ‘0’.

S4525A Peripherals & Enhanced FLASH 13 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 13 Peripherals & Enhanced FLASH FLASH Program Memory: High Voltage ICSP Mode RB6 RB7 PIC16F87X or PIC16F62X V DD CLK DATA PIC16F87X or PIC16F62X enters High Voltage ICSP™ Mode 13V +5V 5V MCLR V DD

S4525A Peripherals & Enhanced FLASH 14 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 14 Peripherals & Enhanced FLASH FLASH Program Memory: High Voltage ICSP Mode Sequence: l V DD and MCLR/V PP are at same voltage. l MCLR/V PP is raised to +13V (High Voltage). l PIC16F87X/PIC16F62X enters High Voltage ICSP mode. In High Voltage ICSP Mode: l RB6 and RB7 are used as serial clock/data to serially program the PIC16F87X /PIC16F62X. l All programming operations are enabled. l If LVP bit = 1, RB3/PGM is available as a normal I/O. l High Voltage ICSP mode can be entered, irrespective of the state of the LVP bit. l LVP bit can only be modified in High Voltage ICSP mode. Sequence: l V DD and MCLR/V PP are at same voltage. l MCLR/V PP is raised to +13V (High Voltage). l PIC16F87X/PIC16F62X enters High Voltage ICSP mode. In High Voltage ICSP Mode: l RB6 and RB7 are used as serial clock/data to serially program the PIC16F87X /PIC16F62X. l All programming operations are enabled. l If LVP bit = 1, RB3/PGM is available as a normal I/O. l High Voltage ICSP mode can be entered, irrespective of the state of the LVP bit. l LVP bit can only be modified in High Voltage ICSP mode.

S4525A Peripherals & Enhanced FLASH 15 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 15 Peripherals & Enhanced FLASH FLASH Program Memory: Internal Program Write Mode l During normal program execution, a device can write to its own program space. l V DD can be at any operating level: 2.0V to 5.5 V. l Erase automatically precedes the write to the word. l Application Usage: l Storing calibration constants for sensors and transducers in program memory. l Field re-calibration of constants. l Remote re-programming of sections of code excluding code protected areas. l Checksum. l Code revisions. l Tech Briefs: TB025 and TB026. l During normal program execution, a device can write to its own program space. l V DD can be at any operating level: 2.0V to 5.5 V. l Erase automatically precedes the write to the word. l Application Usage: l Storing calibration constants for sensors and transducers in program memory. l Field re-calibration of constants. l Remote re-programming of sections of code excluding code protected areas. l Checksum. l Code revisions. l Tech Briefs: TB025 and TB026.

S4525A Peripherals & Enhanced FLASH 16 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 16 Peripherals & Enhanced FLASH FLASH Program Memory: Read/Write Operations Over Voltage l Internal Read/Write Operations: l Can always read any locations at any voltage. l When writes are enabled, can write at any voltage. l External (ICSP) Read/Write Operations: l When enabled: l Read from any location over voltage. l Perform a write to a single location over voltage. l Perform an erase/write cycle to a single location over voltage. l Bulk erase when V DD > 4.5V. l Internal Read/Write Operations: l Can always read any locations at any voltage. l When writes are enabled, can write at any voltage. l External (ICSP) Read/Write Operations: l When enabled: l Read from any location over voltage. l Perform a write to a single location over voltage. l Perform an erase/write cycle to a single location over voltage. l Bulk erase when V DD > 4.5V.

S4525A Peripherals & Enhanced FLASH 17 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 17 Peripherals & Enhanced FLASH Data EEPROM Memory: Reading Locations l Program sequence to read Internal Data EEPROM: l Write the desired address to EEADR. l Clear the EEPGD bit, EECON1, which will select Data EEPROM. l Set the RD bit, EECON1. l Data will be available in the EEDATA register in the next instruction cycle. l Program sequence to read Internal Data EEPROM: l Write the desired address to EEADR. l Clear the EEPGD bit, EECON1, which will select Data EEPROM. l Set the RD bit, EECON1. l Data will be available in the EEDATA register in the next instruction cycle.

S4525A Peripherals & Enhanced FLASH 18 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 18 Peripherals & Enhanced FLASH Data EEPROM Memory: Reading Locations Program: ;Move to Bank2 ;Write data memory address into the EEADR register ;Move to Bank3 ;Point to Data Memory ;Start the Read Operation, data will be available in the very next Tcy ;Move the data into W Program: ;Move to Bank2 ;Write data memory address into the EEADR register ;Move to Bank3 ;Point to Data Memory ;Start the Read Operation, data will be available in the very next Tcy ;Move the data into W BSFSTATUS,RP1 BCFSTATUS,RP0 MOVLWADDRESS MOVWFEEADR BSFSTATUS,RP0 BCFEECON1,EEPGD BSFEECON1,RD BCFSTATUS,RP0 MOVFEEDATA,W

S4525A Peripherals & Enhanced FLASH 19 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 19 Peripherals & Enhanced FLASH Data EEPROM Memory: Writing to Locations l Sequence to write data to Internal Data EEPROM: l Write the desired address to EEADR. l Write the desired data to EEDATA. l Clear the EEPGD bit, EECON1 which will select the data memory access. l Set the WREN bit, EECON1. l Disable all interrupts. l Write 55h followed by AAh to EECON2. l Set the WR bit, EECON1. l Clear the WREN bit, EECON1. l Interrupts can now be enabled. l Wait for WR bit to clear or EEIF to set, which indicates write operation has completed. l Sequence to write data to Internal Data EEPROM: l Write the desired address to EEADR. l Write the desired data to EEDATA. l Clear the EEPGD bit, EECON1 which will select the data memory access. l Set the WREN bit, EECON1. l Disable all interrupts. l Write 55h followed by AAh to EECON2. l Set the WR bit, EECON1. l Clear the WREN bit, EECON1. l Interrupts can now be enabled. l Wait for WR bit to clear or EEIF to set, which indicates write operation has completed.

S4525A Peripherals & Enhanced FLASH 20 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 20 Peripherals & Enhanced FLASH Data EEPROM Memory: Writing to Locations ;Move to Bank2 ;Write desired address to EEADR ;Write desired data to EEDATA ;Move to Bank3 ;Enable EEPROM writes ;Disable interrupts ;Point to data memory ;Next five instructions are required ;sequence to initiate a write sequence ;Initiate the write sequence ;Enable interrupts ;Disable EEPROM writes, does not affect the current write cycle ;Move to Bank2 ;Write desired address to EEADR ;Write desired data to EEDATA ;Move to Bank3 ;Enable EEPROM writes ;Disable interrupts ;Point to data memory ;Next five instructions are required ;sequence to initiate a write sequence ;Initiate the write sequence ;Enable interrupts ;Disable EEPROM writes, does not affect the current write cycle BSFSTATUS,RP1 BCFSTATUS,RP0 MOVLWADDRESS MOVWFEEADR MOVLWVALUE MOVWFEEDATA BSFSTATUS,RP0 BSFEECON1,WREN BCFEECON1,EEPGD BCFINTCON,GIE MOVLW55h MOVWFEECON2 MOVLWAAh MOVWFEECON2 BSFEECON1,WR BSFINTCON,GIE BCFEECON1,WREN

S4525A Peripherals & Enhanced FLASH 21 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 21 Peripherals & Enhanced FLASH FLASH Program Memory: Reading Locations l Write the 8 LSbs of the desired address to EEADR. l Write the 5 MSbs of the desired address to EEADRH. l Set the EEPGD bit, EECON1 to access Program FLASH Memory. l Set the RD bit, EECON1. l Next two instruction must be set as NOPs. l Data will be available in the EEDATH:EEDATA registers in the instruction after the NOPs. l Write the 8 LSbs of the desired address to EEADR. l Write the 5 MSbs of the desired address to EEADRH. l Set the EEPGD bit, EECON1 to access Program FLASH Memory. l Set the RD bit, EECON1. l Next two instruction must be set as NOPs. l Data will be available in the EEDATH:EEDATA registers in the instruction after the NOPs.

S4525A Peripherals & Enhanced FLASH 22 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 22 Peripherals & Enhanced FLASH FLASH Program Memory: Reading Locations ;Move to Bank2 ;Write data memory address into ;the EEADRH:EEADR register ;Point to program memory ;Start the Read Operation, data will ;be available in the third T CY ;Move the data into W ;Move to Bank2 ;Write data memory address into ;the EEADRH:EEADR register ;Point to program memory ;Start the Read Operation, data will ;be available in the third T CY ;Move the data into W BSFSTATUS,RP1 BCFSTATUS,RP0 MOVLWADDRH MOVWFEEADRH MOVLWADDRL MOVWFEEADR BSFSTATUS,RP0 BSFEECON1,EEPGD BSFEECON1,RD NOP BCFSTATUS,RP0 MOVFEEDATA,W MOVWFTemp MOVFEEDATH,W

S4525A Peripherals & Enhanced FLASH 23 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 23 Peripherals & Enhanced FLASH FLASH Program Memory: Writing to Locations l Write the desired address to EEADRH:EEADRL. l Write the desired data to EEDATH:EEDATA. l Set the EEPGD bit, EECON1 to access Program FLASH Memory. l Set the WREN bit, EECON1. l Disable all interrupts. l Write 55h to EECON2 followed by AAh to EECON2. l Set the WR bit, EECON1. l Next two instructions must be NOPs. l CPU now halts while memory is programmed (~2mS), this is NOT sleep mode as the clocks and peripherals continue to run. l When the write is completed, program execution starts at the instruction just after the two NOPs (above). l Clear the WREN bit, EECON1. l Write the desired address to EEADRH:EEADRL. l Write the desired data to EEDATH:EEDATA. l Set the EEPGD bit, EECON1 to access Program FLASH Memory. l Set the WREN bit, EECON1. l Disable all interrupts. l Write 55h to EECON2 followed by AAh to EECON2. l Set the WR bit, EECON1. l Next two instructions must be NOPs. l CPU now halts while memory is programmed (~2mS), this is NOT sleep mode as the clocks and peripherals continue to run. l When the write is completed, program execution starts at the instruction just after the two NOPs (above). l Clear the WREN bit, EECON1.

S4525A Peripherals & Enhanced FLASH 24 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 24 Peripherals & Enhanced FLASH FLASH Program Memory: Writing to Locations ;Move to Bank2 ;Write desired address to EEADRH:EEADR ;Write desired data to EEDATH:EEDATA ;Move to Bank3 ;Enable EEPROM writes ;Point to program memory ;Disable interrupts ;Next five instructions are required ;sequence to initiate a write sequence ;Initiate the write sequence ;Instruction is executed normally ;Instruction is ignored, processor halts ;Enable interrupts ;Disable EEPROM writes ;Move to Bank2 ;Write desired address to EEADRH:EEADR ;Write desired data to EEDATH:EEDATA ;Move to Bank3 ;Enable EEPROM writes ;Point to program memory ;Disable interrupts ;Next five instructions are required ;sequence to initiate a write sequence ;Initiate the write sequence ;Instruction is executed normally ;Instruction is ignored, processor halts ;Enable interrupts ;Disable EEPROM writes BANKSELEEADDRH MOVLWADDRH MOVWFEEADRH MOVLWADDRL MOVWFEEADR MOVLWDATAH MOVWFEEDATH MOVLWDATAL MOVWFEEDATA BSFSTATUS,RP0 BSFEECON1,WREN BSFEECON1,EEPGD BCFINTCON,GIE MOVLW55h MOVWFEECON2 MOVLWAAh MOVWFEECON2 BSFEECON1,WR NOP BSFINTCON,GIE BCFEECON1,WREN

S4525A Peripherals & Enhanced FLASH 25 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 25 Peripherals & Enhanced FLASH Other Programming Options: Using MPLAB  -ICD (In-Circuit Debugger) MPLAB-ICD Module MPLAB-ICD Demo Board Target Socket MPLAB-ICD Header TO RS-232 Power In Target Application or Demo Board

S4525A Peripherals & Enhanced FLASH 26 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 26 Peripherals & Enhanced FLASH MPLAB-ICD: Features l Integrated with MPLAB. l Downloads and executes programs in real time l One selectable breakpoint. l Selectable freeze/unfreeze of peripherals during break. l When break occurs: l Debug software at location 0x1F00 is executed. l Contents of RAM or SFRs can be downloaded to the MPLAB-IDE. l Single stepping of code. l Integrated with MPLAB. l Downloads and executes programs in real time l One selectable breakpoint. l Selectable freeze/unfreeze of peripherals during break. l When break occurs: l Debug software at location 0x1F00 is executed. l Contents of RAM or SFRs can be downloaded to the MPLAB-IDE. l Single stepping of code.

S4525A Peripherals & Enhanced FLASH 27 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 27 Peripherals & Enhanced FLASH MPLAB-ICD: Resources Used on PIC16F87X by ICD l Reset vector location must be a ‘NOP’. l 1 Level of Stack. l Last 256 Words of Program Memory, 1F00h to 1FFFh. l 6 bytes of Data Memory (70h, 1EBh to 1EFh) l Addition of two SFR: l I/O pins RB6 and RB7. l PORTB & TRISB split: l PORTB (006h) & TRISB (086h) control bits 0 to 5. l Reset vector location must be a ‘NOP’. l 1 Level of Stack. l Last 256 Words of Program Memory, 1F00h to 1FFFh. l 6 bytes of Data Memory (70h, 1EBh to 1EFh) l Addition of two SFR: l I/O pins RB6 and RB7. l PORTB & TRISB split: l PORTB (006h) & TRISB (086h) control bits 0 to 5.

S4525A Peripherals & Enhanced FLASH 28 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 28 Peripherals & Enhanced FLASH Reading FLASH Program Memory: Exercise 1 l Access a 7-bit ASCII table without using the RETLW K instruction. l Message located at location 0x500 is: “ Microchip PIC16F87X Demo.” l New MPASM directive {DA “Message”} is used to place the message in program memory. l Message will be retrieved using the FLASH Read operation. l Message will be displayed on the 16x2 Dot Matrix LCD. l Access a 7-bit ASCII table without using the RETLW K instruction. l Message located at location 0x500 is: “ Microchip PIC16F87X Demo.” l New MPASM directive {DA “Message”} is used to place the message in program memory. l Message will be retrieved using the FLASH Read operation. l Message will be displayed on the 16x2 Dot Matrix LCD.

S4525A Peripherals & Enhanced FLASH 29 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 29 Peripherals & Enhanced FLASH Addressable USART: Address Feature l Asynchronous mode, 9-bit reception. l When ADDEN = 1: l RX9 = 1 indicates an address byte. l RSR contents transferred to RCREG FIFO. l Receive interrupt flag set. l RX9 = 0 indicates a data byte. l Reception is ignored. l Interrupt flag not set, next reception overwrites byte. l Asynchronous mode, 9-bit reception. l When ADDEN = 1: l RX9 = 1 indicates an address byte. l RSR contents transferred to RCREG FIFO. l Receive interrupt flag set. l RX9 = 0 indicates a data byte. l Reception is ignored. l Interrupt flag not set, next reception overwrites byte.

S4525A Peripherals & Enhanced FLASH 30 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 30 Peripherals & Enhanced FLASH Addressable USART: Multi-Drop Serial Interface SLAVE 1 PIC16F87X or PIC16F62X SLAVE 2 PIC16F87X or PIC16F62X SLAVE N-1 PIC16F87X or PIC16F62X SLAVE N PIC16F87X or PIC16F62X MASTER PIC16F87X or PIC16F62X 2 Wire RS-485

S4525A Peripherals & Enhanced FLASH 31 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 31 Peripherals & Enhanced FLASH Addressable USART: Multi-Drop Serial Interface l Addressable USART is useful for serial multi-processor communication. l Example: One master, multi-slave, 2-wire RS485 network. l Master transmits packet of data to slaves. l All slave USARTs are in 9-bit mode with the Address Enable Bit (ADDEN) set. l 1st byte has 9th bit set to indicate slave’s address. l Only addressed slave responds by setting its USART to 8 bit mode and ADDEN = 0. l Remaining data bytes in packet have 9th bit clear. l Only addressed slave gets interrupted by the data bytes. l Addressable USART is useful for serial multi-processor communication. l Example: One master, multi-slave, 2-wire RS485 network. l Master transmits packet of data to slaves. l All slave USARTs are in 9-bit mode with the Address Enable Bit (ADDEN) set. l 1st byte has 9th bit set to indicate slave’s address. l Only addressed slave responds by setting its USART to 8 bit mode and ADDEN = 0. l Remaining data bytes in packet have 9th bit clear. l Only addressed slave gets interrupted by the data bytes.

S4525A Peripherals & Enhanced FLASH 32 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 32 Peripherals & Enhanced FLASH Addressable USART: Receive Example b0 b1 b2 b3 b4 b5 b6 b7 b8 RC7/RX Load RSR RCIF ADDEN = 1 RX9 = 0 RSR not loaded RX9 = 1 RSR loaded Data ByteAddress Byte Slave Ignoring Data Packet

S4525A Peripherals & Enhanced FLASH 33 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 33 Peripherals & Enhanced FLASH Addressable USART: Receive Example RX9 = 1 RSR loaded RX9 = 0 RSR loaded Address ByteData Byte b0 b1 b2 b3 b4 b5 b6 b7 b8 RC7/RX Load RSR RCIF ADDEN Slave Accepting Data Packet

S4525A Peripherals & Enhanced FLASH 34 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 34 Peripherals & Enhanced FLASH Addressable USART: Other Features l Dedicated Baud Rate Generator. l Does not utilize timer resources. l Full duplex receive and transmit supported. l Two deep receive buffer. l Transmit is double buffer. l High speed mode allows operation up to 1.25 Mbaud. l Dedicated Baud Rate Generator. l Does not utilize timer resources. l Full duplex receive and transmit supported. l Two deep receive buffer. l Transmit is double buffer. l High speed mode allows operation up to 1.25 Mbaud.

S4525A Peripherals & Enhanced FLASH 35 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 35 Peripherals & Enhanced FLASH TXIF TXIE Interrupt TXEN Baud Rate CLK SPBRG Baud Rate Generator TX9D MSbLSb Data Bus TXREG register TSR register (8) 0 TX9 TRMTSPEN RC6/TX/CK pin Pin Buffer and Control 8  USART Transmit Block Diagram

S4525A Peripherals & Enhanced FLASH 36 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 36 Peripherals & Enhanced FLASH USART Receive Block Diagram x64 Baud Rate CLK SPBRG Baud Rate Generator RC7/RX/DT Pin Buffer and Control SPEN Data Recovery CREN OERR FERR RSR register MSbLSb RX9D RCREG register FIFO Interrupt RCIF RCIE Data Bus 8  64  16 or Stop Start (8) 7 10 RX9 ADDEN RX9 ADDEN RSR Enable Load of Receive Buffer 8 8 

S4525A Peripherals & Enhanced FLASH 37 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 37 Peripherals & Enhanced FLASH 10-Bit A/D Module: Features l PIC16F87X devices have a 10-bit A/D (+/- 1 LSB) l Compatible with 8-bit A/D on PIC16C7X device l ADRES now called ADRESH l New register is added: ADRESL l ADCON0 operates just as in PIC16C7X l There are changes in ADCON1 l A/D conversion between V REF + and V REF - l Min. differential voltage = 2.0V l Conversion in Sleep l Reduces any A/D corruption due to digital “noise” l PIC16F87X devices have a 10-bit A/D (+/- 1 LSB) l Compatible with 8-bit A/D on PIC16C7X device l ADRES now called ADRESH l New register is added: ADRESL l ADCON0 operates just as in PIC16C7X l There are changes in ADCON1 l A/D conversion between V REF + and V REF - l Min. differential voltage = 2.0V l Conversion in Sleep l Reduces any A/D corruption due to digital “noise”

S4525A Peripherals & Enhanced FLASH 38 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 38 Peripherals & Enhanced FLASH 10-Bit A/D Module: Left/Right Justification of A/D Result 10-Bit Result ADFM = 1 ADFM = 0 ADRESHADRESL Bit Result Right Justified ADRESHADRESL 10-Bit Result Left Justified

S4525A Peripherals & Enhanced FLASH 39 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 39 Peripherals & Enhanced FLASH A/D Conversion Timing

S4525A Peripherals & Enhanced FLASH 40 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 40 Peripherals & Enhanced FLASH 10-Bit A/D: Acquisition, Conversion and Sampling Time A/D Sample Time Acquisition Time Conversion Time Go bit set A/D Channel Selected; A/D Turned ON

S4525A Peripherals & Enhanced FLASH 41 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 41 Peripherals & Enhanced FLASH Software Sequence for A/D Conversion l Write to ADCON1 to setup A/D port configuration, VREF selection and 10-bit A/D result format (left or right justified). l Write to ADCON0 to select clock source, ADON and channel selection for A/D conversion. l Allow delay to take care of acquisition time. l Set GO bit in ADCON0. l Test GO bit = 0 for A/D completion. l Read ADRESH and ADRESL for A/D result. l Write to ADCON1 to setup A/D port configuration, VREF selection and 10-bit A/D result format (left or right justified). l Write to ADCON0 to select clock source, ADON and channel selection for A/D conversion. l Allow delay to take care of acquisition time. l Set GO bit in ADCON0. l Test GO bit = 0 for A/D completion. l Read ADRESH and ADRESL for A/D result.

S4525A Peripherals & Enhanced FLASH 42 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 42 Peripherals & Enhanced FLASH 10-Bit A/D: Specifications CharacteristicMinMax Resolution10-bits Integral Linearity Error<+/- 1LSB Differential Linearity Error<+/- 1LSB Offset Error<+/- 1LSB Gain Error<+/- 1LSB Reference Voltage (V REF + - V REF -)2.0VAV DD + 0.3V Reference Voltage HighAV DD - 2.5VAV DD + 0.3V Reference Voltage LowAV SS - 0.3VV REF V Analog Input VoltageAV SS - 0.3VV REF V Target Data: Please check final data sheet/web site for most current data.

S4525A Peripherals & Enhanced FLASH 43 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 43 Peripherals & Enhanced FLASH Master SSP Module: I 2 C  Mode l PIC16F87X devices have the Master SSP. l SSPCON2 register is added. l SSPSTAT are new. l Code from PIC16C7X devices is 100% compatible.

S4525A Peripherals & Enhanced FLASH 44 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 44 Peripherals & Enhanced FLASH I 2 C Master Operation l There is a sequence of events during a transfer from Start bit to Stop bit: Start Bit Byte Writes Byte Reads Acknowledges Restart Conditions Stop Bit l The I 2 C Master is like a state machine. Cannot spool or queue events l The I 2 C module must be idle before starting a new event.

S4525A Peripherals & Enhanced FLASH 45 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 45 Peripherals & Enhanced FLASH I 2 C Master Mode

S4525A Peripherals & Enhanced FLASH 46 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 46 Peripherals & Enhanced FLASH SSP Mode Select Bits SSPM 0000SPI Master Mode, clock = Fosc/4 0001SPI Master Mode, clock = Fosc/ SPI Master Mode, clock = Fosc/ SPI Master Mode, clock = TMR2 output/2 0100SPI Slave Mode, clock = SCK pin, SS enabled 0101SPI Slave Mode, clock = SCK pin, SS disabled 0110I 2 C Slave Mode, 7-bit address 0111I 2 C Slave Mode, 10-bit address 1000I 2 C Master Mode, clock =Fosc/(4*(SSPADD+1)) 1011IC Firmware controlled Master Mode (slave idle) 1110I 2 C Firmware controlled Master Mode, 7-bit address 1111I 2 C Firmware controlled Master Mode, 10-bit address 2

S4525A Peripherals & Enhanced FLASH 47 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 47 Peripherals & Enhanced FLASH Bus Collision l The BCLIF flag bit (PIR2 ) indicates a bus collision. l Always check for bus collision, even if one master and one slave are the only devices on the bus. l Check for bus collision after every idle check. l Make sure that the event has completed and that any possible bus collisions were detected.

S4525A Peripherals & Enhanced FLASH 48 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 48 Peripherals & Enhanced FLASH Write Sequence l Any byte that is written out will generate 9 clocks l 8 clocks for data (SDA is an output). l 1 clock for acknowledge bit (SDA is an input). l State of acknowledge bit is in the ACKSTAT bit (SSPCON2 ). l The state of the acknowledge bit should be checked after idle and bus collision checks. l Write sequence: l Start bit l Control/Address with R/W = 0 l Address byte l Data byte l Stop bit

S4525A Peripherals & Enhanced FLASH 49 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 49 Peripherals & Enhanced FLASH Read Sequence l A read sequence will only generate 8 clocks. l The master must acknowledge the slave. l Write ACK state to ACKDT bit (SSPCON2 ),value used on SDA. l Set the ACKEN bit (SSPCON2 ), starts one clock cycle on SCL. l Read Sequence: l Start bit l Control/Address with R/W = 0 l Address l Restart l Control/Address with R/W = 1 l Read Byte l Stop bit l Last byte read from slave should be NACKed by the master.

S4525A Peripherals & Enhanced FLASH 50 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 50 Peripherals & Enhanced FLASH ACK Polling l Determines if the serial EEPROM can accept more data. l ACK Polling sequence: l Start bit l Control/Address with R/W = 0 l Check to see if the serial EEPROM acknowledged (ACKSTAT = 0) l If serial EEPROM acknowledged then continue l Otherwise, wait for serial EEPROM to acknowledge by: l Restart l Control/Address with R/W = 0 l Check ACKSTAT

S4525A Peripherals & Enhanced FLASH 51 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 51 Peripherals & Enhanced FLASH SPI Mode Block Diagram SPI  Mode Block Diagram

S4525A Peripherals & Enhanced FLASH 52 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 52 Peripherals & Enhanced FLASH SPI Module SCK (CKP = 0,CKE =0) SCK (CKP = 1,CKE =0) SCK (CKP = 0,CKE =1) SCK (CKP = 1,CKE =1) SDO (CKE=0) SDO (CKE=1) SDI (SMP=0) SDI (SMP=1) (Microwire ® ) b7 b6 b5 b4 b3 b2 b1 b0

S4525A Peripherals & Enhanced FLASH 53 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 53 Peripherals & Enhanced FLASH I 2 C Master Mode Exercise 2 l Configure I 2 C module for 100KHz clock. l Read the temperature of the I 2 C sensor DS1721. l Read the temperature 128 times to get an average.

S4525A Peripherals & Enhanced FLASH 54 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 54 Peripherals & Enhanced FLASH Enhanced CCP Module l Capture and Compare Modes: l The same as existing CCP Module. l New PWM Modes: l Single output l Dual outputs l Quad outputs l Capture and Compare Modes: l The same as existing CCP Module. l New PWM Modes: l Single output l Dual outputs l Quad outputs

S4525A Peripherals & Enhanced FLASH 55 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 55 Peripherals & Enhanced FLASH Enhanced CCP Module l Single Output Mode: l PA output running in PWM mode. l Similar to existing CCP in PWM mode. l Selectable active high or active low output. l Application examples: l To create a low frequency D/A converter. l To drive a single power switch. l Single Output Mode: l PA output running in PWM mode. l Similar to existing CCP in PWM mode. l Selectable active high or active low output. l Application examples: l To create a low frequency D/A converter. l To drive a single power switch.

S4525A Peripherals & Enhanced FLASH 56 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 56 Peripherals & Enhanced FLASH Enhanced CCP Module l Dual Output Mode: l PA output running in PWM Mode. l PB output is complementary of PA. l Dead-band control: l To accommodate turn-off delay of one switch before turning on the other. l Programmable times 4xTosc. l Independently selectable active high or active low outputs. l Dual Output Mode: l PA output running in PWM Mode. l PB output is complementary of PA. l Dead-band control: l To accommodate turn-off delay of one switch before turning on the other. l Programmable times 4xTosc. l Independently selectable active high or active low outputs.

S4525A Peripherals & Enhanced FLASH 57 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 57 Peripherals & Enhanced FLASH Dead Time PWM TPTP T DC TDTD T D =Dead Time [Dual Output Mode Only] T DC =Duty Cycle Time T P =Period Time

S4525A Peripherals & Enhanced FLASH 58 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 58 Peripherals & Enhanced FLASH Enhanced CCP Module l Application Examples for Dual Output Mode: l Half-bridge l Full-bridge with all four switches modulated at PWM frequency l Application Examples for Dual Output Mode: l Half-bridge l Full-bridge with all four switches modulated at PWM frequency

S4525A Peripherals & Enhanced FLASH 59 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 59 Peripherals & Enhanced FLASH PWM Dual Output Mode Half Bridge Example LOAD FET DRIVER PA PB PIC16C717 PIC16C770 PIC16C771

S4525A Peripherals & Enhanced FLASH 60 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 60 Peripherals & Enhanced FLASH PWM Dual Output Mode Full Bridge Example PA PB PIC16C717 PIC16C770 PIC16C771 V HIGH FET DRIVER FET DRIVER MOTOR PIC16C717 PIC16C770 PIC16C771 PA PB FET DRIVER

S4525A Peripherals & Enhanced FLASH 61 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 61 Peripherals & Enhanced FLASH Enhanced CCP Module l Quad Output Mode: l PB or PD output modulated. l PC or PA output is active. l Independently selectable active high or active low output pairs. l Application Examples: l Full-bridge where only one switch is modulated at PWM frequency to minimize switching losses. l Quad Output Mode: l PB or PD output modulated. l PC or PA output is active. l Independently selectable active high or active low output pairs. l Application Examples: l Full-bridge where only one switch is modulated at PWM frequency to minimize switching losses.

S4525A Peripherals & Enhanced FLASH 62 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 62 Peripherals & Enhanced FLASH PWM Quad Output Mode Example FET DRIVER PA PB PC PD PIC16C717 PIC16C770 PIC16C771 MOTOR V HIGH FET DRIVER A C BD

S4525A Peripherals & Enhanced FLASH 63 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 63 Peripherals & Enhanced FLASH Bank0 Bank1 Bank2 Bank3Bank0 Bank1 Special Function Registers PIC16C74BPIC16F874 00h 1Fh 80h 9Fh 180h 19Fh

S4525A Peripherals & Enhanced FLASH 64 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 64 Peripherals & Enhanced FLASH PINOUT MCLR/VPP RB7 RA0/AN0 RB6 RA1/AN1 RB5 RA2/AN2 RB4 RA3/AN3/VREF RB3 RA4/T0CKI RB2 RA5/SS/AN4 RB1 RE0/RD/AN5 RB0/INT RE1/WR/AN6 V DD RE2/CS/AN7 V SS V DD RD7/PSP7 V SS RD6/PSP6 OSC1/CLKIN RD5/PSP5 OSC2/CLKOUT RD4/PSP4 RC0/T1OSO/T1CKI RC7/RX/DT RC1/T1OSI/CCP2 RC6/TX/CK RC2/CCP1 RC5/SDO RC3/SCK/SCL RC4/SDI/SDA RD0/PSP0 RD3/PSP3 RD1/PSP1 RD2/PSP2 PIC16C74B RA2/AN2/V REF - RA3/AN3/V REF + RB7/PGD RB6/PGC RB3/PGM PIC16F874

S4525A Peripherals & Enhanced FLASH 65 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 65 Peripherals & Enhanced FLASH Feature Comparison DevicePIC16C74APIC16C74BPIC16F874PIC16C77PIC16F877 Operating Freq.DC-20MHz Resets/DelaysPOR,BOR PWRT,OST Prog. Mem4K EPROM 4K FLASH8K EPROM8K FLASH Data Mem EEPROM Interrupts I/O Ports33 Timers33333 CCP22222 SPIYYY, Enh. I2CSlave Mstr/SlaveSlaveMstr/Slave USARTYYY, 9-bitY Parallel PortYYYYY 8-bit A/D8 ch. 10-bit A/D8 ch. ICSP/ICDY/N Y/YY/NY/Y

S4525A Peripherals & Enhanced FLASH 66 © 1999 Microchip Technology Incorporated. All Rights Reserved. S4525A Peripherals & Enhanced FLASH 66 Peripherals & Enhanced FLASH Bank0 Bank1 Bank2 Bank3 Special Function Registers PIC16C77 PIC16F877 00h 180h 1Fh 19Fh 00h 1Fh 180h 19Fh